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Message-ID: <20250915163637.3572-2-biju.das.jz@bp.renesas.com>
Date: Mon, 15 Sep 2025 17:36:30 +0100
From: Biju <biju.das.au@...il.com>
To: Uwe Kleine-König <ukleinek@...nel.org>
Cc: Biju Das <biju.das.jz@...renesas.com>,
linux-pwm@...r.kernel.org,
linux-kernel@...r.kernel.org,
Geert Uytterhoeven <geert+renesas@...der.be>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>,
Biju Das <biju.das.au@...il.com>,
linux-renesas-soc@...r.kernel.org
Subject: [PATCH v3 1/2] pwm: rzg2l-gpt: Reinitialize cache value
From: Biju Das <biju.das.jz@...renesas.com>
Reinitialize the cache value to 0 during disable().
Fixes: 061f087f5d0b ("pwm: Add support for RZ/G2L GPT")
Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
---
v3:
* New patch.
---
drivers/pwm/pwm-rzg2l-gpt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
index 360c8bf3b190..b2452e50d618 100644
--- a/drivers/pwm/pwm-rzg2l-gpt.c
+++ b/drivers/pwm/pwm-rzg2l-gpt.c
@@ -190,8 +190,10 @@ static void rzg2l_gpt_disable(struct rzg2l_gpt_chip *rzg2l_gpt,
/* Stop count, Output low on GTIOCx pin when counting stops */
rzg2l_gpt->channel_enable_count[ch]--;
- if (!rzg2l_gpt->channel_enable_count[ch])
+ if (!rzg2l_gpt->channel_enable_count[ch]) {
rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_CST, 0);
+ rzg2l_gpt->period_ticks[ch] = 0;
+ }
/* Disable pin output */
rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTIOR(ch), RZG2L_GTIOR_OxE(sub_ch), 0);
--
2.43.0
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