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Message-ID: <aMhSbIvjwz2J4KCx@x1>
Date: Mon, 15 Sep 2025 10:52:44 -0700
From: Drew Fustini <fustini@...nel.org>
To: Conor Dooley <conor@...nel.org>
Cc: Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Alexandre Ghiti <alex@...ti.fr>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Samuel Holland <samuel.holland@...ive.com>,
	Daniel Lezcano <daniel.lezcano@...aro.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Anup Patel <anup@...infault.org>, Arnd Bergmann <arnd@...db.de>,
	Joel Stanley <jms@...storrent.com>, Joel Stanley <joel@....id.au>,
	Michael Neuling <mikey@...ling.org>,
	Nicholas Piggin <npiggin@...il.com>,
	Michael Ellerman <mpe@...nel.org>, Andy Gross <agross@...nel.org>,
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org, Drew Fustini <dfustini@...storrent.com>
Subject: Re: [PATCH 7/7] riscv: Kconfig.socs: Add ARCH_TENSTORRENT for
 Tenstorrent SoCs

On Mon, Sep 15, 2025 at 05:48:06PM +0100, Conor Dooley wrote:
> On Sat, Sep 13, 2025 at 02:31:06PM -0700, Drew Fustini wrote:
> > From: Drew Fustini <dfustini@...storrent.com>
> > 
> > Add Kconfig option ARCH_TENSTORRENT to enable support for SoCs like the
> > Blackhole A0.
> > 
> > Signed-off-by: Drew Fustini <dfustini@...storrent.com>
> > ---
> >  arch/riscv/Kconfig.socs | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> > 
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index 61ceae0aa27a6fa3a91da6a46becfd96da99fd09..ff733a998612d429e7b1e00276eb86290d8331a3 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -57,6 +57,14 @@ config ARCH_SUNXI
> >  	  This enables support for Allwinner sun20i platform hardware,
> >  	  including boards based on the D1 and D1s SoCs.
> >  
> > +config ARCH_TENSTORRENT
> > +	bool "Tenstorrent SoCs"
> > +	help
> > +	  This enables support for Tenstorrent SoC platforms.
> > +	  Current support is for Blackhole P100 and P150 PCIe cards.
> > +	  The Blackhole A0 SoC contains four RISC-V CPU tiles each
> > +	  consisting of 4x SiFive X280 cores.
> 
> Can you add this to defconfig too, so that it gets build by default in
> that configuration?

Sure, will do.

Thanks,
Drew

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