linux-kernel - Re: [PATCH v6 0/8] Add SBI v3.0 PMU enhancements

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Message-ID: <CAAhSdy3wJd5uicJntf+WgTaLciiQsqT1QfUmrZ1Jk9qEONRgPw@mail.gmail.com>
Date: Mon, 15 Sep 2025 17:28:48 +0530
From: Anup Patel <anup@...infault.org>
To: Will Deacon <will@...nel.org>
Cc: Paul Walmsley <pjw@...nel.org>, Atish Patra <atishp@...osinc.com>, 
	Mark Rutland <mark.rutland@....com>, Paul Walmsley <paul.walmsley@...ive.com>, 
	Palmer Dabbelt <palmer@...belt.com>, Mayuresh Chitale <mchitale@...tanamicro.com>, 
	linux-riscv@...ts.infradead.org, linux-arm-kernel@...ts.infradead.org, 
	linux-kernel@...r.kernel.org, kvm@...r.kernel.org, 
	kvm-riscv@...ts.infradead.org, Sean Christopherson <seanjc@...gle.com>
Subject: Re: [PATCH v6 0/8] Add SBI v3.0 PMU enhancements

Hi Will,

On Mon, Sep 15, 2025 at 4:11 PM Will Deacon <will@...nel.org> wrote:
>
> On Mon, Sep 15, 2025 at 12:25:52AM -0600, Paul Walmsley wrote:
> > On Tue, 9 Sep 2025, Atish Patra wrote:
> >
> > > SBI v3.0 specification[1] added two new improvements to the PMU chaper.
> > > The SBI v3.0 specification is frozen and under public review phase as
> > > per the RISC-V International guidelines.
> > >
> > > 1. Added an additional get_event_info function to query event availablity
> > > in bulk instead of individual SBI calls for each event. This helps in
> > > improving the boot time.
> > >
> > > 2. Raw event width allowed by the platform is widened to have 56 bits
> > > with RAW event v2 as per new clarification in the priv ISA[2].
> > >
> > > Apart from implementing these new features, this series improves the gpa
> > > range check in KVM and updates the kvm SBI implementation to SBI v3.0.
> > >
> > > The opensbi patches have been merged. This series can be found at [3].
> > >
> > > [1] https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0-rc7/riscv-sbi.pdf
> > > [2] https://github.com/riscv/riscv-isa-manual/issues/1578
> > > [3] https://github.com/atishp04/linux/tree/b4/pmu_event_info_v6
> > >
> > > Signed-off-by: Atish Patra <atishp@...osinc.com>
> >
> > For the series:
> >
> > Acked-by: Paul Walmsley <pjw@...nel.org>
>
> I was assuming this series would go via the Risc-V arch tree so please
> shout if you were expecting me to take it via drivers/perf/!
>

Based on offline discussion with Paul, I will take this series
through the KVM RISC-V tree.

Regards,
Anup