linux-kernel - Re: [PATCH 0/2] PCI/ASPM: Enable ASPM and Clock PM by default on devicetree platforms

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Message-ID: <20250916202550.GA1814752@bhelgaas>
Date: Tue, 16 Sep 2025 15:25:50 -0500
From: Bjorn Helgaas <helgaas@...nel.org>
To: manivannan.sadhasivam@....qualcomm.com
Cc: Bjorn Helgaas <bhelgaas@...gle.com>,
	Manivannan Sadhasivam <mani@...nel.org>,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Krzysztof Wilczyński <kwilczynski@...nel.org>,
	Rob Herring <robh@...nel.org>, linux-pci@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
	"David E. Box" <david.e.box@...ux.intel.com>,
	Kai-Heng Feng <kai.heng.feng@...onical.com>,
	"Rafael J. Wysocki" <rafael@...nel.org>,
	Heiner Kallweit <hkallweit1@...il.com>,
	Chia-Lin Kao <acelan.kao@...onical.com>
Subject: Re: [PATCH 0/2] PCI/ASPM: Enable ASPM and Clock PM by default on
 devicetree platforms

[+cc Heiner, AceLan in case it's of interest to you]

On Tue, Sep 16, 2025 at 12:21:18PM -0500, Bjorn Helgaas wrote:
> [+cc Kai-Heng, Rafael; thread at
> https://lore.kernel.org/r/20250916-pci-dt-aspm-v1-0-778fe907c9ad@oss.qualcomm.com]
> 
> On Tue, Sep 16, 2025 at 09:42:51PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> > Hi,
> > 
> > This series is one of the 'let's bite the bullet' kind, where we have decided to
> > enable all ASPM and Clock PM states by default on devicetree platforms [1]. The
> > reason why devicetree platforms were chosen because, it will be of minimal
> > impact compared to the ACPI platforms. So seemed ideal to test the waters.
> > 
> > Problem Statement
> > =================
> > 
> > Historically, PCI subsystem relied on the BIOS to enable ASPM and Clock PM
> > states for PCI devices before the kernel boot. This was done to avoid enabling
> > ASPM for the buggy devices that are known to create issues with ASPM (even
> > though they advertise the ASPM capability). But BIOS is not at all a thing on
> > most of the non-x86 platforms. For instance, the majority of the Embedded and
> > Compute ARM based platforms using devicetree have something called bootloader,
> > which is not anyway near the standard BIOS used in x86 based platforms. And
> > these bootloaders wouldn't touch PCIe at all, unless they boot using PCIe
> > storage, even then there would be no guarantee that the ASPM states will get
> > enabled. Another example is the Intel's VMD domain that is not at all configured
> > by the BIOS. But, this series is not enabling ASPM/Clock PM for VMD domain. I
> > hope it will be done similarly in the future patches.
> > 
> > Solution
> > ========
> > 
> > So to avoid relying on BIOS, it was agreed [2] that the PCI subsystem has to
> > enable ASPM and Clock PM states based on the device capability. If any devices
> > misbehave, then they should be quirked accordingly.
> > 
> > First patch of this series introduces two helper functions to enable all ASPM
> > and Clock PM states if CONFIG_OF is enabled. Second patch drops the custom ASPM
> > enablement code from the pcie-qcom driver as it is no longer needed.
> > 
> > Testing
> > =======
> > 
> > This series is tested on Lenovo Thinkpad T14s based on Snapdragon X1 SoC. All
> > supported ASPM states are getting enabled for both the NVMe and WLAN devices by
> > default.
> > 
> > [1] https://lore.kernel.org/linux-pci/a47sg5ahflhvzyzqnfxvpk3dw4clkhqlhznjxzwqpf4nyjx5dk@bcghz5o6zolk
> > [2] https://lore.kernel.org/linux-pci/20250828204345.GA958461@bhelgaas
> > 
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>
> > ---
> > Manivannan Sadhasivam (2):
> >       PCI/ASPM: Override the ASPM and Clock PM states set by BIOS for devicetree platforms
> >       PCI: qcom: Remove the custom ASPM enablement code
> > 
> >  drivers/pci/controller/dwc/pcie-qcom.c | 32 -----------------------
> >  drivers/pci/pcie/aspm.c                | 48 ++++++++++++++++++++++++++++++----
> >  2 files changed, 43 insertions(+), 37 deletions(-)
> > ---
> > base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585
> > change-id: 20250916-pci-dt-aspm-8b3a7e8d2cf1
> > 
> > Best regards,
> > -- 
> > Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>
> > 
> >