| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <CAKfTPtDog36hBZ0XvhC-NyfL0SwB5ve53nLFpofToKt1ebhuGQ@mail.gmail.com>
Date: Tue, 16 Sep 2025 10:10:31 +0200
From: Vincent Guittot <vincent.guittot@...aro.org>
To: Bjorn Helgaas <helgaas@...nel.org>
Cc: chester62515@...il.com, mbrugger@...e.com, ghennadi.procopciuc@....nxp.com,
s32@....com, lpieralisi@...nel.org, kwilczynski@...nel.org, mani@...nel.org,
robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
Ionut.Vicovan@....com, larisa.grigore@....com, Ghennadi.Procopciuc@....com,
ciprianmarian.costea@....com, bogdan.hamciuc@....com,
linux-arm-kernel@...ts.infradead.org, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/4] dt-bindings: pcie: Add the NXP PCIe controller
On Sun, 14 Sept 2025 at 14:35, Vincent Guittot
<vincent.guittot@...aro.org> wrote:
>
> On Sat, 13 Sept 2025 at 00:50, Bjorn Helgaas <helgaas@...nel.org> wrote:
> >
> > On Fri, Sep 12, 2025 at 04:14:33PM +0200, Vincent Guittot wrote:
> > > Describe the PCIe controller available on the S32G platforms.
> > >
> > > Co-developed-by: Ionut Vicovan <Ionut.Vicovan@....com>
> > > Signed-off-by: Ionut Vicovan <Ionut.Vicovan@....com>
> > > Co-developed-by: Bogdan-Gabriel Roman <bogdan-gabriel.roman@....com>
> > > Signed-off-by: Bogdan-Gabriel Roman <bogdan-gabriel.roman@....com>
> > > Co-developed-by: Larisa Grigore <larisa.grigore@....com>
> > > Signed-off-by: Larisa Grigore <larisa.grigore@....com>
> > > Co-developed-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@....com>
> > > Signed-off-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@....com>
> > > Co-developed-by: Ciprian Marian Costea <ciprianmarian.costea@....com>
> > > Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@....com>
> > > Co-developed-by: Bogdan Hamciuc <bogdan.hamciuc@....com>
> > > Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@....com>
> > > Signed-off-by: Vincent Guittot <vincent.guittot@...aro.org>
> > > ---
> > > .../devicetree/bindings/pci/nxp,s32-pcie.yaml | 169 ++++++++++++++++++
> > > 1 file changed, 169 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/pci/nxp,s32-pcie.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/pci/nxp,s32-pcie.yaml b/Documentation/devicetree/bindings/pci/nxp,s32-pcie.yaml
> > > new file mode 100644
> > > index 000000000000..287596d7162d
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/pci/nxp,s32-pcie.yaml
> > > @@ -0,0 +1,169 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/pci/nxp,s32-pcie.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: NXP S32G2xx/S32G3xx PCIe controller
> > > +
> > > +maintainers:
> > > + - Bogdan Hamciuc <bogdan.hamciuc@....com>
> > > + - Ionut Vicovan <ionut.vicovan@....com>
> > > +
> > > +description:
> > > + This PCIe controller is based on the Synopsys DesignWare PCIe IP.
> > > + The S32G SoC family has two PCIe controllers, which can be configured as
> > > + either Root Complex or End Point.
> >
> > s/End Point/Endpoint/ to match spec usage.
>
> Ok
>
> >
> > > +properties:
> > > + compatible:
> > > + oneOf:
> > > + - enum:
> > > + - nxp,s32g2-pcie # S32G2 SoCs RC mode
> > > + - items:
> > > + - const: nxp,s32g3-pcie
> > > + - const: nxp,s32g2-pcie
> > > +
> > > + reg:
> > > + minItems: 7
> > > + maxItems: 7
> > > +
> > > + reg-names:
> > > + items:
> > > + - const: dbi
> > > + - const: dbi2
> > > + - const: atu
> > > + - const: dma
> > > + - const: ctrl
> > > + - const: config
> > > + - const: addr_space
> > > +
> > > + interrupts:
> > > + minItems: 8
> > > + maxItems: 8
> > > +
> > > + interrupt-names:
> > > + items:
> > > + - const: link_req_stat
> > > + - const: dma
> > > + - const: msi
> > > + - const: phy_link_down
> > > + - const: phy_link_up
> > > + - const: misc
> > > + - const: pcs
> > > + - const: tlp_req_no_comp
> > > +
> > > + msi-parent:
> > > + description:
> > > + Use this option to reference the GIC controller node which will
> > > + handle the MSIs. This property can be used only in Root Complex mode.
> > > + The msi-parent node must be declared as "msi-controller" and the list of
> > > + available SPIs that can be used must be declared using "mbi-ranges".
> > > + If "msi-parent" is not present in the PCIe node, MSIs will be handled
> > > + by iMSI-RX -Integrated MSI Receiver [AXI Bridge]-, an integrated
> > > + MSI reception module in the PCIe controller's AXI Bridge which
> > > + detects and terminates inbound MSI requests (received on the RX wire).
> > > + These MSIs no longer appear on the AXI bus, instead a hard-wired
> > > + interrupt is raised, documented as "DSP AXI MSI Interrupt" in the SoC
> > > + Reference Manual.
> > > +
> > > + nxp,phy-mode:
> > > + $ref: /schemas/types.yaml#/definitions/string
> > > + description: Select PHY mode for PCIe controller
> > > + enum:
> > > + - crns # Common Reference Clock, No Spread Spectrum
> > > + - crss # Common Reference Clock, Spread Spectrum
> > > + - srns # Separate reference Clock, No Spread Spectrum
> > > + - sris # Separate Reference Clock, Independent Spread Spectrum
> > > +
> > > + max-link-speed:
> > > + description:
> > > + The max link speed is normaly Gen3, but can be enforced to a lower value
> > > + in case of special limitations.
> >
> > s/normaly/normally/
> >
> > But I doubt you need this here at all.
>
> I'm going to remove the description
>
> >
> > > + maximum: 3
> > > +
> > > + num-lanes:
> > > + description:
> > > + Max bus width (1 or 2); it is the number of physical lanes
> > > + minimum: 1
> > > + maximum: 2
> > > +
> > > +allOf:
> > > + - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - reg-names
> > > + - interrupts
> > > + - interrupt-names
> > > + - ranges
> > > + - nxp,phy-mode
> > > + - num-lanes
> > > + - phys
> > > +
> > > +additionalProperties: true
> > > +
> > > +examples:
> > > + - |
> > > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > + #include <dt-bindings/phy/phy.h>
> > > +
> > > + bus {
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > +
> > > + pcie0: pcie@...00000 {
> > > + compatible = "nxp,s32g3-pcie",
> > > + "nxp,s32g2-pcie";
> > > + dma-coherent;
> > > + reg = <0x00 0x40400000 0x0 0x00001000>, /* dbi registers */
> > > + <0x00 0x40420000 0x0 0x00001000>, /* dbi2 registers */
> > > + <0x00 0x40460000 0x0 0x00001000>, /* atu registers */
> > > + <0x00 0x40470000 0x0 0x00001000>, /* dma registers */
> > > + <0x00 0x40481000 0x0 0x000000f8>, /* ctrl registers */
> > > + /* RC configuration space, 4KB each for cfg0 and cfg1
> > > + * at the end of the outbound memory map
> > > + */
> > > + <0x5f 0xffffe000 0x0 0x00002000>,
> > > + <0x58 0x00000000 0x0 0x40000000>; /* 1GB EP addr space */
> > > + reg-names = "dbi", "dbi2", "atu", "dma", "ctrl",
> > > + "config", "addr_space";
> > > + #address-cells = <3>;
> > > + #size-cells = <2>;
> > > + device_type = "pci";
> > > + ranges =
> > > + /* downstream I/O, 64KB and aligned naturally just
> > > + * before the config space to minimize fragmentation
> > > + */
> > > + <0x81000000 0x0 0x00000000 0x5f 0xfffe0000 0x0 0x00010000>,
> > > + /* non-prefetchable memory, with best case size and
> > > + * alignment
> > > + */
> > > + <0x82000000 0x0 0x00000000 0x58 0x00000000 0x7 0xfffe0000>;
> > > +
> > > + nxp,phy-mode = "crns";
> > > + bus-range = <0x0 0xff>;
> > > + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
> > > + interrupt-names = "link_req_stat", "dma", "msi",
> > > + "phy_link_down", "phy_link_up", "misc",
> > > + "pcs", "tlp_req_no_comp";
> > > + #interrupt-cells = <1>;
> > > + interrupt-map-mask = <0 0 0 0x7>;
> > > + interrupt-map = <0 0 0 1 &gic 0 0 0 128 4>,
> > > + <0 0 0 2 &gic 0 0 0 129 4>,
> > > + <0 0 0 3 &gic 0 0 0 130 4>,
> > > + <0 0 0 4 &gic 0 0 0 131 4>;
> > > + msi-parent = <&gic>;
> > > +
> > > + num-lanes = <2>;
> > > + phys = <&serdes0 PHY_TYPE_PCIE 0 0>;
> >
> > num-lanes and phys are properties of a Root Port, not the host bridge.
> > Please put them in a separate stanza. See this for details and
> > examples:
> >
> > https://lore.kernel.org/linux-pci/20250625221653.GA1590146@bhelgaas/
>
> Ok, I'm going to have a look
This driver relies on dw_pcie_host_init() to get common resources like
num-lane which doesn't look at childs to get num-lane.
I have to keep num-lane in the pcie node. Having this in mind should I
keep phys as well as they are both linked ?
>
> >
> > > + };
> > > + };
> > > --
> > > 2.43.0
> > >
Powered by blists - more mailing lists