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Message-ID: <5e94042f.9278.1995203a448.Coremail.andyshrk@163.com>
Date: Tue, 16 Sep 2025 18:13:14 +0800 (CST)
From: "Andy Yan" <andyshrk@....com>
To: "Quentin Schulz" <quentin.schulz@...rry.de>
Cc: "Quentin Schulz" <quentin.schulz@...rry.de>,
"Chaoyi Chen" <kernel@...kyi.com>,
"Heiko Stuebner" <heiko@...ech.de>,
"Andy Yan" <andy.yan@...k-chips.com>,
"Rob Herring" <robh@...nel.org>,
"Krzysztof Kozlowski" <krzk+dt@...nel.org>,
"Conor Dooley" <conor+dt@...nel.org>,
"Dragan Simic" <dsimic@...jaro.org>,
"FUKAUMI Naoki" <naoki@...xa.com>, "Jonas Karlman" <jonas@...boo.se>,
"Peter Robinson" <pbrobinson@...il.com>,
"chaoyi.chen@...k-chips.com" <chaoyi.chen@...k-chips.com>,
"Geert Uytterhoeven" <geert+renesas@...der.be>,
"Cristian Ciocaltea" <cristian.ciocaltea@...labora.com>,
"Sebastian Reichel" <sebastian.reichel@...labora.com>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re:Re: [PATCH] arm64: dts: rockchip: Enable DisplayPort for
rk3588-evb2
Hello Quentin，
在 2025-09-16 17:48:41，"Chaoyi Chen" <chaoyi.chen@...k-chips.com> 写道：
>On 9/16/2025 5:24 PM, Quentin Schulz wrote:
>
>> On 9/16/25 11:18 AM, Chaoyi Chen wrote:
>>> Hi Quentin,
>>>
>>> On 9/16/2025 4:41 PM, Quentin Schulz wrote:
>>>> Hi Chaoyi Chen,
>>>>
>>>> On 9/16/25 10:08 AM, Chaoyi Chen wrote:
>>>>> From: Chaoyi Chen <chaoyi.chen@...k-chips.com>
>>>>>
>>>>> The rk3588 evb2 board has a full size DisplayPort connector, enable
>>>>> for it.
>>>>>
>>>>> Signed-off-by: Chaoyi Chen <chaoyi.chen@...k-chips.com>
>>>>> ---
>>>>> .../boot/dts/rockchip/rk3588-evb2-v10.dts | 39 +++++++++++++++++++
>>>>> 1 file changed, 39 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts b/arch/ arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
>>>>> index 91fe810d38d8..0e5af61f66fe 100644
>>>>> --- a/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
>>>>> +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
>>>>> @@ -25,6 +25,18 @@ chosen {
>>>>> stdout-path = "serial2:1500000n8";
>>>>> };
>>>>> + dp-con {
>>>>> + compatible = "dp-connector";
>>>>> + label = "DP OUT";
>>>>> + type = "full size";
>>>>
>>>> This isn't valid according to the dt binding. It should be "full-size" instead.
>>>
>>> Will fix in v2.
>>>
>>>
>>>>
>>>>> +
>>>>> + port {
>>>>> + dp_con_in: endpoint {
>>>>> + remote-endpoint = <&dp0_out_con>;
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> hdmi-con {
>>>>> compatible = "hdmi-connector";
>>>>> type = "a";
>>>>> @@ -106,6 +118,24 @@ vcc5v0_usbdcin: regulator-vcc5v0-usbdcin {
>>>>> };
>>>>> };
>>>>> +&dp0 {
>>>>> + pinctrl-0 = <&dp0m0_pins>;
>>>>> + pinctrl-names = "default";
>>>>> + status = "okay";
>>>>> +};
>>>>> +
>>>>> +&dp0_in {
>>>>> + dp0_in_vp2: endpoint {
>>>>> + remote-endpoint = <&vp2_out_dp0>;
>>>>> + };
>>>>> +};
>>>>> +
>>>>> +&dp0_out {
>>>>> + dp0_out_con: endpoint {
>>>>> + remote-endpoint = <&dp_con_in>;
>>>>> + };
>>>>> +};
>>>>> +
>>>>> &gpu {
>>>>> mali-supply = <&vdd_gpu_s0>;
>>>>> sram-supply = <&vdd_gpu_mem_s0>;
>>>>> @@ -916,6 +946,8 @@ &usb_host1_xhci {
>>>>> };
>>>>> &vop {
>>>>> + assigned-clocks = <&cru DCLK_VOP2_SRC>;
>>>>> + assigned-clock-parents = <&cru PLL_V0PLL>;
>>>>
>>>> This is surprising, the only other board which has the DP0 enabled (the CoolPi 4B) doesn't set these two.
>>>>
>>>> Does HDMI still work as well as it used to with these new properties? Why are those needed? Some context in the commit log or as a comment in the DT would be most welcome!
>>>
>>> Yes, HDMI and DP can work normally whether these new properties removed or not.
>>>
>>> The key point is that when using V0PLL, we can get more usable resolution because DP requires a precise clock. If V0PLL is not explicitly specified here, then dclk_vop2 (VP2) may be divided down on GPLL, CPLL, etc. In this case, only a few frequency points are available. In my case, when V0PLL is not used, only resolutions such as 1024x768 and 640x480 are available.
>
>Oh! This is because GPLL was not initialized to the correct frequency during the U-Boot stage. It should support typical frequencies such as 1080P (148.5M), 4K (594M) .
>
>
>>>
>>> For HDMI, I think it will use clk_hdmiphy_pixel0/1 as clock parent which is provided by the HDMI PHY when it work on TMDS mode so that we don't need to set it .
>>>
>>
>> Considering the clocks are all internal to the SoC, shouldn't all you have explained be applicable to the CoolPi 4B too (and other boards with DP)? I'm trying to understand if we should add something similar to CoolPi 4B DTS as well?
>
>Yes, I think this modification is necessary because some resolutions use special frequencies.
>
>
>>
>> @Andy, you're the one who added support for DP to CoolPi 4B, without these properties, is there something we need to do there as well?
On the CoolPI 4B, since no dedicated PLL was specified, the GPLL would be automatically assigned as the PLL source for dclk_vop2.
As the frequency of GPLL is 1188 MHz, we can only get typical clock frequencies such as 74.25, 148.5, 297, 594MHz, which correspond
to typical resolutions of 720P, 1080P, 4K30/60. If there are some more special resolutions, such as a 3840x2160 59.94Hz DP resolution
that requires a dclk clock of 593.407 MHz, then it cannot be supported.
I will conduct more tests later and then submit a patch to specify V0PLL for CoolPi 4B's VP2.
And Chaoyi's patch is correct.
>>
>> Thanks!
>> Quentin
>>
>>
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