linux-kernel - Re: [PATCH 1/4] dt-bindings: pcie: Add the NXP PCIe controller

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Message-ID: <e236uncj7qradf34elkmd2c4wjogc6pfkobuu7muyoyb2hrrai@tta36jq5fzsr>
Date: Wed, 17 Sep 2025 22:41:08 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Bjorn Helgaas <helgaas@...nel.org>
Cc: Vincent Guittot <vincent.guittot@...aro.org>, 
	Jingoo Han <jingoohan1@...il.com>, chester62515@...il.com, mbrugger@...e.com, 
	ghennadi.procopciuc@....nxp.com, s32@....com, lpieralisi@...nel.org, kwilczynski@...nel.org, 
	robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org, Ionut.Vicovan@....com, 
	larisa.grigore@....com, Ghennadi.Procopciuc@....com, ciprianmarian.costea@....com, 
	bogdan.hamciuc@....com, linux-arm-kernel@...ts.infradead.org, linux-pci@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/4] dt-bindings: pcie: Add the NXP PCIe controller

On Tue, Sep 16, 2025 at 09:23:13AM GMT, Bjorn Helgaas wrote:
> On Tue, Sep 16, 2025 at 10:10:31AM +0200, Vincent Guittot wrote:
> > On Sun, 14 Sept 2025 at 14:35, Vincent Guittot
> > <vincent.guittot@...aro.org> wrote:
> > > On Sat, 13 Sept 2025 at 00:50, Bjorn Helgaas <helgaas@...nel.org> wrote:
> > > > On Fri, Sep 12, 2025 at 04:14:33PM +0200, Vincent Guittot wrote:
> > > > > Describe the PCIe controller available on the S32G platforms.
> 
> > > > > +                  num-lanes = <2>;
> > > > > +                  phys = <&serdes0 PHY_TYPE_PCIE 0 0>;
> > > >
> > > > num-lanes and phys are properties of a Root Port, not the host bridge.
> > > > Please put them in a separate stanza.  See this for details and
> > > > examples:
> > > >
> > > >   https://lore.kernel.org/linux-pci/20250625221653.GA1590146@bhelgaas/
> > >
> > > Ok, I'm going to have a look
> > 
> > This driver relies on dw_pcie_host_init() to get common resources like
> > num-lane which doesn't look at childs to get num-lane.
> > 
> > I have to keep num-lane in the pcie node. Having this in mind should I
> > keep phys as well as they are both linked ?
> 
> Huh, that sounds like an issue in the DWC core.  Jingoo, Mani?
> 
> dw_pcie_host_init() includes several things that assume a single Root
> Port: num_lanes, of_pci_get_equalization_presets(),
> dw_pcie_start_link() are all per-Root Port things.
> 

Yeah, it is a gap right now. We only recently started moving the DWC platforms
to per Root Port binding (like Qcom).

Unfortunately, I don't have cycles for it atleast this week.

- Mani

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