linux-kernel - Re: [PATCH v3 3/4] PCI: qcom: Parse PERST# from all PCIe bridge nodes

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Message-ID: <vlpsaepw33ffv2mtenpkmsdtuf3aofxgi37utzqfxddervo32x@notmpwk44fej>
Date: Wed, 17 Sep 2025 15:38:48 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: Bjorn Helgaas <helgaas@...nel.org>
Cc: manivannan.sadhasivam@....qualcomm.com, 
	Lorenzo Pieralisi <lpieralisi@...nel.org>, Krzysztof Wilczyński <kwilczynski@...nel.org>, 
	Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>, 
	Bartosz Golaszewski <brgl@...ev.pl>, Saravana Kannan <saravanak@...gle.com>, 
	linux-pci@...r.kernel.org, linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org, 
	devicetree@...r.kernel.org, Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>, 
	Brian Norris <briannorris@...omium.org>
Subject: Re: [PATCH v3 3/4] PCI: qcom: Parse PERST# from all PCIe bridge nodes

On Tue, Sep 16, 2025 at 02:49:06PM GMT, Bjorn Helgaas wrote:
> On Mon, Sep 15, 2025 at 06:23:45PM +0530, Manivannan Sadhasivam wrote:
> > On Fri, Sep 12, 2025 at 06:28:11PM GMT, Bjorn Helgaas wrote:
> > > On Fri, Sep 12, 2025 at 02:05:03PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> > > > From: Manivannan Sadhasivam <manivannan.sadhasivam@....qualcomm.com>
> > > > 
> > > > Devicetree schema allows the PERST# GPIO to be present in all
> > > > PCIe bridge nodes, not just in Root Port node. But the current
> > > > logic parses PERST# only from the Root Port nodes. Though it is
> > > > not causing any issue on the current platforms, the upcoming
> > > > platforms will have PERST# in PCIe switch downstream ports also.
> > > > So this requires parsing all the PCIe bridge nodes for the
> > > > PERST# GPIO.
> > > > 
> > > > Hence, rework the parsing logic to extend to all PCIe bridge
> > > > nodes starting from the Root Port node. If the 'reset-gpios'
> > > > property is found for a PCI bridge node, the GPIO descriptor
> > > > will be stored in qcom_pcie_perst::desc and added to the
> > > > qcom_pcie_port::perst list.
> > > 
> > > The switch part doesn't seem qcom specific.  Aren't we going to
> > > end up with lots of drivers reimplementing something like the
> > > qcom_pcie_port.perst list?
> > 
> > If this kind of switch is attached to other platforms, then yes.
> > Right now, Qcom host is the only known DT based host platform that
> > has seen this requirement.
> 
> So I guess the issue here is that pwrctrl controls power to a slot
> below a Switch Downstream Port, and we want pwrctrl to also control
> PERST# to that same slot so that pwrctrl can power up the slot and
> then deassert PERST# to the slot later, e.g., after a T_PVPERL delay?
> 
> Seems like whatever parses the devicetree power regulator information
> for the slot should also parse the PERST# GPIO for the slot.
> 

Problem is, the controller driver also asserts PERST# during controller
initialization. So even if the power control driver parses PERST#, it still need
to share it with the controller driver somehow. I tried it in previous
iteration, but it turned out to be too complex. So settled with this version
where the controller driver parses PERST# as it used to, but not just from Root
Port and then asserts/deasserts PERST# through the callback.

- Mani

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