linux-kernel - Re: [PATCH v2 3/3] arm64: dts: add Protonic PRT8ML board

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Message-ID: <20250918165156.10e55b85@erd003.prtnl>
Date: Thu, 18 Sep 2025 16:51:56 +0200
From: David Jander <david@...tonic.nl>
To: Andrew Lunn <andrew@...n.ch>
Cc: Jonas Rebmann <jre@...gutronix.de>, Vladimir Oltean <olteanv@...il.com>,
 "David S. Miller" <davem@...emloft.net>, Eric Dumazet
 <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni
 <pabeni@...hat.com>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski
 <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Liam Girdwood
 <lgirdwood@...il.com>, Mark Brown <broonie@...nel.org>, Shengjiu Wang
 <shengjiu.wang@....com>, Shawn Guo <shawnguo@...nel.org>, Sascha Hauer
 <s.hauer@...gutronix.de>, Fabio Estevam <festevam@...il.com>, Pengutronix
 Kernel Team <kernel@...gutronix.de>, Vladimir Oltean
 <vladimir.oltean@....com>, netdev@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-sound@...r.kernel.org, imx@...ts.linux.dev,
 linux-arm-kernel@...ts.infradead.org, Lucas Stach <l.stach@...gutronix.de>,
 Oleksij Rempel <o.rempel@...gutronix.de>
Subject: Re: [PATCH v2 3/3] arm64: dts: add Protonic PRT8ML board

On Thu, 18 Sep 2025 16:14:28 +0200
Andrew Lunn <andrew@...n.ch> wrote:

> > +			port@4 {
> > +				reg = <4>;
> > +				ethernet = <&fec>;
> > +				label = "cpu";
> > +				phy-mode = "rgmii-id";
> > +				rx-internal-delay-ps = <2000>;
> > +				tx-internal-delay-ps = <2000>;
> > +
> > +				fixed-link {
> > +					full-duplex;
> > +					speed = <100>;
> > +				};
> > +			};
> > +		};
> > +	};
> > +};
> > +
> > +&fec {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_fec>;
> > +	phy-mode = "rgmii"; /* switch inserts delay */
> > +	rx-internal-delay-ps = <0>;
> > +	tx-internal-delay-ps = <0>;
> > +	status = "okay";
> > +
> > +	fixed-link {
> > +		full-duplex;
> > +		speed = <100>;
> > +	};  
> 
> You have an RGMII interface, but you run it at 100Mbps? That might be
> worth a comment somewhere to explain why.

Yes, unfortunately the SJA1105Q does not support PAUSE frames, and the i.MX8MP
FEC isn't able to sustain 1000Mbps (only about 400ish) due to insufficient
internal bus bandwidth. It will generate PAUSE frames, but the SJA1105Q
ignores these, leading to packet loss, which is obviously worse than
restricting this link to 100Mbps. Ironically both chips are from the same
manufacturer, yet are incompatible in this regard.

Best regards,

-- 
David Jander