linux-kernel - Re: [PATCH v3 6/8] dt-bindings: soc: renesas: Add the Renesas RZ/N1 GPIO Interrupt Multiplexer

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Message-ID: <20250918-majestic-mockup-0a0e090db0a7@spud>
Date: Thu, 18 Sep 2025 16:06:04 +0100
From: Conor Dooley <conor@...nel.org>
To: "Herve Codina (Schneider Electric)" <herve.codina@...tlin.com>
Cc: Thomas Gleixner <tglx@...utronix.de>,
	Wolfram Sang <wsa+renesas@...g-engineering.com>,
	Hoan Tran <hoan@...amperecomputing.com>,
	Linus Walleij <linus.walleij@...aro.org>,
	Bartosz Golaszewski <brgl@...ev.pl>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Magnus Damm <magnus.damm@...il.com>,
	Saravana Kannan <saravanak@...gle.com>,
	Serge Semin <fancer.lancer@...il.com>,
	Phil Edworthy <phil.edworthy@...esas.com>,
	linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
	Pascal Eberhard <pascal.eberhard@...com>,
	Miquel Raynal <miquel.raynal@...tlin.com>,
	Thomas Petazzoni <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH v3 6/8] dt-bindings: soc: renesas: Add the Renesas RZ/N1
 GPIO Interrupt Multiplexer

On Thu, Sep 18, 2025 at 12:40:04PM +0200, Herve Codina (Schneider Electric) wrote:
> On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those
> interruption lines are multiplexed by the GPIO Interrupt Multiplexer in
> order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.
> 
> The GPIO interrupt multiplexer IP does nothing but select 8 GPIO
> IRQ lines out of the 96 available to wire them to the GIC input lines.
> 
> Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@...tlin.com>
> ---
>  .../soc/renesas/renesas,rzn1-gpioirqmux.yaml  | 87 +++++++++++++++++++
>  1 file changed, 87 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml

This is an interrupt controller, please move it to that subdirectory.
Otherwise,
Acked-by: Conor Dooley <conor.dooley@...rochip.com>

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