Message-ID: <20250918201430.GA1919478@bhelgaas>
Date: Thu, 18 Sep 2025 15:14:30 -0500
From: Bjorn Helgaas <helgaas@...nel.org>
To: Ziyue Zhang <ziyue.zhang@....qualcomm.com>
Cc: andersson@...nel.org, konradybcio@...nel.org, robh@...nel.org,
	krzk+dt@...nel.org, conor+dt@...nel.org, jingoohan1@...il.com,
	mani@...nel.org, lpieralisi@...nel.org, kwilczynski@...nel.org,
	bhelgaas@...gle.com, johan+linaro@...nel.org, vkoul@...nel.org,
	kishon@...nel.org, neil.armstrong@...aro.org, abel.vesa@...aro.org,
	kw@...ux.com, linux-arm-msm@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-pci@...r.kernel.org, linux-phy@...ts.infradead.org,
	qiang.yu@....qualcomm.com, quic_krichai@...cinc.com,
	quic_vbadigan@...cinc.com, Ziyue Zhang <quic_ziyuzhan@...cinc.com>
Subject: Re: [PATCH v13 0/5] pci: qcom: Add QCS8300 PCIe support

On Thu, Sep 18, 2025 at 10:51:22AM +0800, Ziyue Zhang wrote:
> On 9/8/2025 3:38 PM, Ziyue Zhang wrote:
> > This series depend on this patch
> > https://lore.kernel.org/all/20250826-pakala-v2-3-74f1f60676c6@oss.qualcomm.com/

That patch ("PCI: qcom: Restrict port parsing only to pci child
nodes") is currently in the pci/controller/qcom branch:

  https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/log/?h=controller/qcom

and won't be merged upstream until the v6.18 merge window.  This will
probably be between Sep 28 and Oct 12.

I don't know what that means for the dt-binding and arm64 dts changes
in this series, but typically changes like this series are merged via
a different tree than the PCI changes, so the ordering isn't
guaranteed until one of them is pulled by Linus.

> > This series adds document, phy, configs support for PCIe in QCS8300.
> > It also adds 'link_down' reset for sa8775p.
> > 
> > Have follwing changes:
> > 	- Add dedicated schema for the PCIe controllers found on QCS8300.
> > 	- Add compatible for qcs8300 platform.
> > 	- Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence.
> > 	- Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence.
> > 
> > Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
> > Signed-off-by: Ziyue Zhang <quic_ziyuzhan@...cinc.com>
> > ---
> > Changes in v13:
> > - Fix dtb error
> > - Link to v12: https://lore.kernel.org/all/20250905071448.2034594-1-ziyue.zhang@oss.qualcomm.com/
> > 
> > Changes in v12:
> > - rebased pcie phy bindings
> > - Link to v11: https://lore.kernel.org/all/20250826091205.3625138-1-ziyue.zhang@oss.qualcomm.com/
> > 
> > Changes in v11:
> > - move phy/perst/wake to pcie bridge node (Mani)
> > - Link to v10: https://lore.kernel.org/all/20250811071131.982983-1-ziyue.zhang@oss.qualcomm.com/
> > 
> > Changes in v10:
> > - Update PHY max_items (Johan)
> > - Link to v9: https://lore.kernel.org/all/20250725104037.4054070-1-ziyue.zhang@oss.qualcomm.com/
> > 
> > Changes in v9:
> > - Fix DTB error (Vinod)
> > - Link to v8: https://lore.kernel.org/all/20250714081529.3847385-1-ziyue.zhang@oss.qualcomm.com/
> > 
> > Changes in v8:
> > - rebase sc8280xp-qmp-pcie-phy change to solve conflicts.
> > - Add Fixes tag to phy change (Johan)
> > - Link to v7: https://lore.kernel.org/all/20250625092539.762075-1-quic_ziyuzhan@quicinc.com/
> > 
> > Changes in v7:
> > - rebase qcs8300-ride.dtsi change to solve conflicts.
> > - Link to v6: https://lore.kernel.org/all/20250529035635.4162149-1-quic_ziyuzhan@quicinc.com/
> > 
> > Changes in v6:
> > - move the qcs8300 and sa8775p phy compatibility entry into the list of PHYs that require six clocks
> > - Update QCS8300 and sa8775p phy dt, remove aux clock.
> > - Fixed compile error found by kernel test robot
> > - Link to v5: https://lore.kernel.org/all/20250507031019.4080541-1-quic_ziyuzhan@quicinc.com/
> > 
> > Changes in v5:
> > - Add QCOM PCIe controller version in commit msg (Mani)
> > - Modify platform dts change subject (Dmitry)
> > - Fixed compile error found by kernel test robot
> > - Link to v4: https://lore.kernel.org/linux-phy/20241220055239.2744024-1-quic_ziyuzhan@quicinc.com/
> > 
> > Changes in v4:
> > - Add received tag
> > - Fixed compile error found by kernel test robot
> > - Link to v3: https://lore.kernel.org/lkml/202412211301.bQO6vXpo-lkp@intel.com/T/#mdd63e5be39acbf879218aef91c87b12d4540e0f7
> > 
> > Changes in v3:
> > - Add received tag(Rob & Dmitry)
> > - Update pcie_phy in gcc node to soc dtsi(Dmitry & Konrad)
> > - remove pcieprot0 node(Konrad & Mani)
> > - Fix format comments(Konrad)
> > - Update base-commit to tag: next-20241213(Bjorn)
> > - Corrected of_device_id.data from 1.9.0 to 1.34.0.
> > - Link to v2: https://lore.kernel.org/all/20241128081056.1361739-1-quic_ziyuzhan@quicinc.com/
> > 
> > Changes in v2:
> > - Fix some format comments and match the style in x1e80100(Konrad)
> > - Add global interrupt for PCIe0 and PCIe1(Konrad)
> > - split the soc dtsi and the platform dts into two changes(Konrad)
> > - Link to v1: https://lore.kernel.org/all/20241114095409.2682558-1-quic_ziyuzhan@quicinc.com/
> > 
> > Ziyue Zhang (5):
> >    dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings
> >      for qcs8300
> >    arm64: dts: qcom: qcs8300: enable pcie0
> >    arm64: dts: qcom: qcs8300-ride: enable pcie0 interface
> >    arm64: dts: qcom: qcs8300: enable pcie1
> >    arm64: dts: qcom: qcs8300-ride: enable pcie1 interface
> > 
> >   .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml       |  17 +-
> >   arch/arm64/boot/dts/qcom/qcs8300-ride.dts     |  84 +++++
> >   arch/arm64/boot/dts/qcom/qcs8300.dtsi         | 310 +++++++++++++++++-
> >   3 files changed, 394 insertions(+), 17 deletions(-)
> > 
> > 
> > base-commit: be5d4872e528796df9d7425f2bd9b3893eb3a42c
> Hi Maintainers,
> 
> It seems the patches get reviewed tag for a long time, can you give this
> 
> series further comment or help me to merge them ?
> Thanks very much.
> 
> BRs
> Ziyue
> 
> -- 
> linux-phy mailing list
> linux-phy@...ts.infradead.org
> https://lists.infradead.org/mailman/listinfo/linux-phy

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