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Message-ID: <20250918091023.GC23028@nxa18884-linux.ap.freescale.net>
Date: Thu, 18 Sep 2025 17:10:23 +0800
From: Peng Fan <peng.fan@....nxp.com>
To: Tim Harvey <tharvey@...eworks.com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, devicetree@...r.kernel.org,
imx@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/7] arm64: dts: imx8mp-venice-gw702x: reduce RGMII CLK
drive strength
Hi Tim,
On Tue, Sep 16, 2025 at 08:32:12AM -0700, Tim Harvey wrote:
>The i.MX8M Plus EQOS RGMII tracelength is less than 1in and does not
>require a x6 drive strength. Reduce the CLK drive strength to x1 for
>better emissions.
>
>Signed-off-by: Tim Harvey <tharvey@...eworks.com>
>---
> arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi
>index a1232a4f8485..dd9eeb3479fd 100644
>--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi
>+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi
>@@ -462,7 +462,7 @@ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
> MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
> MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
> MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
>- MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
>+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x0
You also changed FSEL from 2 to 0. So I would add this in commit that if this
matches:
Since TXC is not a high frequency clock, use slow slew rate for lower emissions
and better signal quality
Regards
Peng
> >;
> };
>
>--
>2.25.1
>
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