linux-kernel - Re: [PATCH] arm64/mm: Elide TLB flush in certain pte protection transitions

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Message-ID: <41443985-341b-4139-ab20-be2ac96e31d4@arm.com>
Date: Thu, 18 Sep 2025 18:16:47 +0530
From: Dev Jain <dev.jain@....com>
To: Kefeng Wang <wangkefeng.wang@...wei.com>, catalin.marinas@....com,
 will@...nel.org
Cc: anshuman.khandual@....com, ryan.roberts@....com, baohua@...nel.org,
 pjaroszynski@...dia.com, linux-arm-kernel@...ts.infradead.org,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64/mm: Elide TLB flush in certain pte protection
 transitions


On 18/09/25 5:52 pm, Kefeng Wang wrote:
>
>
> On 2025/9/18 18:36, Dev Jain wrote:
>> Currently arm64 does an unconditional TLB flush in mprotect(). This 
>> is not
>> required for some cases, for example, when changing from PROT_NONE to
>> PROT_READ | PROT_WRITE (a real usecase - glibc malloc does this to 
>> emulate
>> growing into the non-main heaps), and unsetting uffd-wp in a range.
>>
>> Therefore, implement pte_needs_flush() for arm64, which is already
>> implemented by some other arches as well.
>>
>> Running a userspace program changing permissions back and forth between
>> PROT_NONE and PROT_READ | PROT_WRITE, and measuring the average time 
>> taken
>> for the none->rw transition, I get a reduction from 3.2 microseconds to
>> 2.95 microseconds, giving an 8.5% improvement.
>>
>
> Hi Dev，
>
>> Signed-off-by: Dev Jain <dev.jain@....com>
>> ---
>> mm-selftests pass. Based on 6.17-rc6.
>>
>>   arch/arm64/include/asm/tlbflush.h | 29 +++++++++++++++++++++++++++++
>>   1 file changed, 29 insertions(+)
>>
>> diff --git a/arch/arm64/include/asm/tlbflush.h 
>> b/arch/arm64/include/asm/tlbflush.h
>> index 18a5dc0c9a54..4a566d589100 100644
>> --- a/arch/arm64/include/asm/tlbflush.h
>> +++ b/arch/arm64/include/asm/tlbflush.h
>> @@ -524,6 +524,35 @@ static inline void 
>> arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *b
>>   {
>>       __flush_tlb_range_nosync(mm, start, end, PAGE_SIZE, true, 3);
>>   }
>> +
>> +static inline bool __pte_flags_need_flush(pteval_t oldval, pteval_t 
>> newval)
>> +{
>> +    pteval_t diff = oldval ^ newval;
>> +
>> +    /* invalid to valid transition requires no flush */
>> +    if (!(oldval & PTE_VALID) || (oldval & PTE_PRESENT_INVALID))
>> +        return false;
>> +
>> +    /* Transition in the SW bits and access flag requires no flush */
>> +    diff &= ~(PTE_SWBITS_MASK | PTE_AF);
>> +
>> +    if (!diff)
>> +        return false;
>> +    return true;
>> +}
>> +
>
> LibMicro mprotect testcase show 3~5% improvement with different size in
> old kernel(we did this before, but only check PTE_VALID and 
> PTE_PROT_NONE in our kernel), it seems that no one change other sw bit 
> by mprotect?

Not mprotect, but when unsetting uffd-wp, we do mwriteprotect_range -> 
uffd_wp_range -> change_protection() with MM_CP_UFFD_WP_RESOLVE set.


>
> Anyway, Reviewed-by: Kefeng Wang <wangkefeng.wang@...wei.com>

Thanks!


>
>> +static inline bool pte_needs_flush(pte_t oldpte, pte_t newpte)
>> +{
>> +    return __pte_flags_need_flush(pte_val(oldpte), pte_val(newpte));
>> +}
>> +#define pte_needs_flush pte_needs_flush
>> +
>> +static inline bool huge_pmd_needs_flush(pmd_t oldpmd, pmd_t newpmd)
>> +{
>> +    return __pte_flags_need_flush(pmd_val(oldpmd), pmd_val(newpmd));
>> +}
>> +#define huge_pmd_needs_flush huge_pmd_needs_flush
>> +
>>   #endif
>>     #endif
>