linux-kernel - Re: [PATCH v9 01/10] x86/cpufeatures: Add support for L3 Smart Data Cache Injection Allocation Enforcement

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Message-ID: <55592492-bd86-45dd-8262-a34bc74d849f@amd.com>
Date: Fri, 19 Sep 2025 10:45:09 -0500
From: "Moger, Babu" <bmoger@....com>
To: Reinette Chatre <reinette.chatre@...el.com>,
 Babu Moger <babu.moger@....com>, corbet@....net, tony.luck@...el.com,
 Dave.Martin@....com, james.morse@....com, tglx@...utronix.de,
 mingo@...hat.com, bp@...en8.de, dave.hansen@...ux.intel.com
Cc: x86@...nel.org, hpa@...or.com, kas@...nel.org,
 rick.p.edgecombe@...el.com, akpm@...ux-foundation.org, paulmck@...nel.org,
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Subject: Re: [PATCH v9 01/10] x86/cpufeatures: Add support for L3 Smart Data
 Cache Injection Allocation Enforcement

Hi Reinette,

Thanks for the review of the series. Sorry for duplicate messages. 
Setting the email on my new machine.

On 9/18/2025 12:08 AM, Reinette Chatre wrote:
> Hi Babu,
> 
> (Just highlighting some changelog formatting that was needed for ABMC
> changelogs.)
> 
> On 9/2/25 3:41 PM, Babu Moger wrote:
>> Smart Data Cache Injection (SDCI) is a mechanism that enables direct
>> insertion of data from I/O devices into the L3 cache. By directly caching
>> data from I/O devices rather than first storing the I/O data in DRAM,
>> SDCI reduces demands on DRAM bandwidth and reduces latency to the processor
>> consuming the I/O data.
>>
>> The SDCIAE (SDCI Allocation Enforcement) PQE feature allows system software
>> to control the portion of the L3 cache used for SDCI.
>>
>> When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache
>> partitions identified by the highest-supported L3_MASK_n register, where n
>> is the maximum supported CLOSID.
>>
>> Add CPUID feature bit that can be used to configure SDCIAE.
>>
>> The SDCIAE feature details are documented in APM [1] available from [2].
>> [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
>> Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache
>> Injection Allocation Enforcement (SDCIAE)
> 
> Compare with how indentation of ABMC "x86,fs/resctrl: Implement resctrl_arch_config_cntr()
> to assign a counter with ABMC" was changed during merge.
> 
>    [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
>        Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache
>        Injection Allocation Enforcement (SDCIAE)
> 
> (also applies to patch #4)

Sure.

> 
>>
>> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 # [2]
> 
> Please place "Link:" tag at end to reduce needed adjustments during
> merge.
> 

Yes. Sure.

Kept the Acked-by and Reviewed-by tag as is.

Thanks

Babu