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Message-ID: <20250919195326.2079446-1-robh@kernel.org>
Date: Fri, 19 Sep 2025 14:53:24 -0500
From: "Rob Herring (Arm)" <robh@...nel.org>
To: Stefan Schaeckeler <sschaeck@...co.com>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Joel Stanley <joel@....id.au>,
Andrew Jeffery <andrew@...econstruct.com.au>
Cc: devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-aspeed@...ts.ozlabs.org,
linux-kernel@...r.kernel.org
Subject: [PATCH] dt-bindings: edac: Convert aspeed,ast2400-sdram-edac to DT schema
Convert the ASpeed SDRAM EDAC binding to DT schema. It's a
straight-forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@...nel.org>
---
.../edac/aspeed,ast2400-sdram-edac.yaml | 48 +++++++++++++++++++
.../bindings/edac/aspeed-sdram-edac.txt | 28 -----------
MAINTAINERS | 2 +-
3 files changed, 49 insertions(+), 29 deletions(-)
create mode 100644 Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml
delete mode 100644 Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
diff --git a/Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml b/Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml
new file mode 100644
index 000000000000..09735826d707
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/edac/aspeed,ast2400-sdram-edac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed BMC SoC SDRAM EDAC controller
+
+maintainers:
+ - Stefan Schaeckeler <sschaeck@...co.com>
+
+description: >
+ The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
+ correction check).
+
+ The memory controller supports SECDED (single bit error correction, double bit
+ error detection) and single bit error auto scrubbing by reserving 8 bits for
+ every 64 bit word (effectively reducing available memory to 8/9).
+
+ Note, the bootloader must configure ECC mode in the memory controller.
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2400-sdram-edac
+ - aspeed,ast2500-sdram-edac
+ - aspeed,ast2600-sdram-edac
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ sdram@...e0000 {
+ compatible = "aspeed,ast2500-sdram-edac";
+ reg = <0x1e6e0000 0x174>;
+ interrupts = <0>;
+ };
diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
deleted file mode 100644
index 8ca9e0a049d8..000000000000
--- a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-Aspeed BMC SoC EDAC node
-
-The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
-correction check).
-
-The memory controller supports SECDED (single bit error correction, double bit
-error detection) and single bit error auto scrubbing by reserving 8 bits for
-every 64 bit word (effectively reducing available memory to 8/9).
-
-Note, the bootloader must configure ECC mode in the memory controller.
-
-
-Required properties:
-- compatible: should be one of
- - "aspeed,ast2400-sdram-edac"
- - "aspeed,ast2500-sdram-edac"
- - "aspeed,ast2600-sdram-edac"
-- reg: sdram controller register set should be <0x1e6e0000 0x174>
-- interrupts: should be AVIC interrupt #0
-
-
-Example:
-
- edac: sdram@...e0000 {
- compatible = "aspeed,ast2500-sdram-edac";
- reg = <0x1e6e0000 0x174>;
- interrupts = <0>;
- };
diff --git a/MAINTAINERS b/MAINTAINERS
index ec0aba646e7e..b6800e86286a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8848,7 +8848,7 @@ F: drivers/edac/armada_xp_*
EDAC-AST2500
M: Stefan Schaeckeler <sschaeck@...co.com>
S: Supported
-F: Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt
+F: Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml
F: drivers/edac/aspeed_edac.c
EDAC-BLUEFIELD
--
2.51.0
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