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Message-ID: <20250919195400.3180039-2-ovidiu.panait.oss@gmail.com>
Date: Fri, 19 Sep 2025 22:53:56 +0300
From: Ovidiu Panait <ovidiu.panait.oss@...il.com>
To: gregkh@...uxfoundation.org,
linux-kernel@...r.kernel.org,
linux-staging@...ts.linux.dev
Cc: Ovidiu Panait <ovidiu.panait.oss@...il.com>
Subject: [PATCH 2/6] staging: axis-fifo: simplify interrupt handling
The irq handler iterates through the interrupt bits one by one in a while()
loop, clearing one bit at a time. This is unnecessary and inefficient, as
the 'Interrupt Status Register' can be cleared with a single write
operation.
Also the irq handler checks for some interrupts that are masked out in the
'Interrupt Enable Register', so they are never triggered.
Simplify the irq handler by removing the checks for interrupts that are
masked out and clear the whole 'Interrupt Status Register' in one go. The
macros that are no longer relevant are also removed.
Signed-off-by: Ovidiu Panait <ovidiu.panait.oss@...il.com>
---
drivers/staging/axis-fifo/axis-fifo.c | 144 ++++++--------------------
1 file changed, 33 insertions(+), 111 deletions(-)
diff --git a/drivers/staging/axis-fifo/axis-fifo.c b/drivers/staging/axis-fifo/axis-fifo.c
index bab2002628df..33a8440858d9 100644
--- a/drivers/staging/axis-fifo/axis-fifo.c
+++ b/drivers/staging/axis-fifo/axis-fifo.c
@@ -89,16 +89,8 @@
#define XLLF_INT_TC_MASK 0x08000000 /* Transmit complete */
#define XLLF_INT_RC_MASK 0x04000000 /* Receive complete */
#define XLLF_INT_TSE_MASK 0x02000000 /* Transmit length mismatch */
-#define XLLF_INT_TRC_MASK 0x01000000 /* Transmit reset complete */
-#define XLLF_INT_RRC_MASK 0x00800000 /* Receive reset complete */
-#define XLLF_INT_TFPF_MASK 0x00400000 /* Tx FIFO Programmable Full */
-#define XLLF_INT_TFPE_MASK 0x00200000 /* Tx FIFO Programmable Empty */
-#define XLLF_INT_RFPF_MASK 0x00100000 /* Rx FIFO Programmable Full */
-#define XLLF_INT_RFPE_MASK 0x00080000 /* Rx FIFO Programmable Empty */
-#define XLLF_INT_ALL_MASK 0xfff80000 /* All the ints */
-#define XLLF_INT_ERROR_MASK 0xf2000000 /* Error status ints */
-#define XLLF_INT_RXERROR_MASK 0xe0000000 /* Receive Error status ints */
-#define XLLF_INT_TXERROR_MASK 0x12000000 /* Transmit Error status ints */
+
+#define XLLF_INT_CLEAR_ALL GENMASK(31, 0)
/* ----------------------------
* globals
@@ -166,7 +158,7 @@ static void reset_ip_core(struct axis_fifo *fifo)
XLLF_INT_RPORE_MASK | XLLF_INT_RPUE_MASK |
XLLF_INT_TPOE_MASK | XLLF_INT_TSE_MASK,
fifo->base_addr + XLLF_IER_OFFSET);
- iowrite32(XLLF_INT_ALL_MASK, fifo->base_addr + XLLF_ISR_OFFSET);
+ iowrite32(XLLF_INT_CLEAR_ALL, fifo->base_addr + XLLF_ISR_OFFSET);
}
/**
@@ -402,106 +394,36 @@ static ssize_t axis_fifo_write(struct file *f, const char __user *buf,
static irqreturn_t axis_fifo_irq(int irq, void *dw)
{
- struct axis_fifo *fifo = (struct axis_fifo *)dw;
- unsigned int pending_interrupts;
-
- do {
- pending_interrupts = ioread32(fifo->base_addr +
- XLLF_IER_OFFSET) &
- ioread32(fifo->base_addr
- + XLLF_ISR_OFFSET);
- if (pending_interrupts & XLLF_INT_RC_MASK) {
- /* packet received */
-
- /* wake the reader process if it is waiting */
- wake_up(&fifo->read_queue);
-
- /* clear interrupt */
- iowrite32(XLLF_INT_RC_MASK & XLLF_INT_ALL_MASK,
- fifo->base_addr + XLLF_ISR_OFFSET);
- } else if (pending_interrupts & XLLF_INT_TC_MASK) {
- /* packet sent */
-
- /* wake the writer process if it is waiting */
- wake_up(&fifo->write_queue);
-
- iowrite32(XLLF_INT_TC_MASK & XLLF_INT_ALL_MASK,
- fifo->base_addr + XLLF_ISR_OFFSET);
- } else if (pending_interrupts & XLLF_INT_TFPF_MASK) {
- /* transmit fifo programmable full */
-
- iowrite32(XLLF_INT_TFPF_MASK & XLLF_INT_ALL_MASK,
- fifo->base_addr + XLLF_ISR_OFFSET);
- } else if (pending_interrupts & XLLF_INT_TFPE_MASK) {
- /* transmit fifo programmable empty */
-
- iowrite32(XLLF_INT_TFPE_MASK & XLLF_INT_ALL_MASK,
- fifo->base_addr + XLLF_ISR_OFFSET);
- } else if (pending_interrupts & XLLF_INT_RFPF_MASK) {
- /* receive fifo programmable full */
-
- iowrite32(XLLF_INT_RFPF_MASK & XLLF_INT_ALL_MASK,
- fifo->base_addr + XLLF_ISR_OFFSET);
- } else if (pending_interrupts & XLLF_INT_RFPE_MASK) {
- /* receive fifo programmable empty */
-
- iowrite32(XLLF_INT_RFPE_MASK & XLLF_INT_ALL_MASK,
- fifo->base_addr + XLLF_ISR_OFFSET);
- } else if (pending_interrupts & XLLF_INT_TRC_MASK) {
- /* transmit reset complete interrupt */
-
- iowrite32(XLLF_INT_TRC_MASK & XLLF_INT_ALL_MASK,
- fifo->base_addr + XLLF_ISR_OFFSET);
- } else if (pending_interrupts & XLLF_INT_RRC_MASK) {
- /* receive reset complete interrupt */
-
- iowrite32(XLLF_INT_RRC_MASK & XLLF_INT_ALL_MASK,
- fifo->base_addr + XLLF_ISR_OFFSET);
- } else if (pending_interrupts & XLLF_INT_RPURE_MASK) {
- /* receive fifo under-read error interrupt */
- dev_err(fifo->dt_device,
- "receive under-read interrupt\n");
-
- iowrite32(XLLF_INT_RPURE_MASK & XLLF_INT_ALL_MASK,
- fifo->base_addr + XLLF_ISR_OFFSET);
- } else if (pending_interrupts & XLLF_INT_RPORE_MASK) {
- /* receive over-read error interrupt */
- dev_err(fifo->dt_device,
- "receive over-read interrupt\n");
-
- iowrite32(XLLF_INT_RPORE_MASK & XLLF_INT_ALL_MASK,
- fifo->base_addr + XLLF_ISR_OFFSET);
- } else if (pending_interrupts & XLLF_INT_RPUE_MASK) {
- /* receive underrun error interrupt */
- dev_err(fifo->dt_device,
- "receive underrun error interrupt\n");
-
- iowrite32(XLLF_INT_RPUE_MASK & XLLF_INT_ALL_MASK,
- fifo->base_addr + XLLF_ISR_OFFSET);
- } else if (pending_interrupts & XLLF_INT_TPOE_MASK) {
- /* transmit overrun error interrupt */
- dev_err(fifo->dt_device,
- "transmit overrun error interrupt\n");
-
- iowrite32(XLLF_INT_TPOE_MASK & XLLF_INT_ALL_MASK,
- fifo->base_addr + XLLF_ISR_OFFSET);
- } else if (pending_interrupts & XLLF_INT_TSE_MASK) {
- /* transmit length mismatch error interrupt */
- dev_err(fifo->dt_device,
- "transmit length mismatch error interrupt\n");
-
- iowrite32(XLLF_INT_TSE_MASK & XLLF_INT_ALL_MASK,
- fifo->base_addr + XLLF_ISR_OFFSET);
- } else if (pending_interrupts) {
- /* unknown interrupt type */
- dev_err(fifo->dt_device,
- "unknown interrupt(s) 0x%x\n",
- pending_interrupts);
-
- iowrite32(XLLF_INT_ALL_MASK,
- fifo->base_addr + XLLF_ISR_OFFSET);
- }
- } while (pending_interrupts);
+ struct axis_fifo *fifo = dw;
+ u32 isr, ier, intr;
+
+ ier = ioread32(fifo->base_addr + XLLF_IER_OFFSET);
+ isr = ioread32(fifo->base_addr + XLLF_ISR_OFFSET);
+ intr = ier & isr;
+
+ if (intr & XLLF_INT_RC_MASK)
+ wake_up(&fifo->read_queue);
+
+ if (intr & XLLF_INT_TC_MASK)
+ wake_up(&fifo->write_queue);
+
+ if (intr & XLLF_INT_RPURE_MASK)
+ dev_err(fifo->dt_device, "receive under-read interrupt\n");
+
+ if (intr & XLLF_INT_RPORE_MASK)
+ dev_err(fifo->dt_device, "receive over-read interrupt\n");
+
+ if (intr & XLLF_INT_RPUE_MASK)
+ dev_err(fifo->dt_device, "receive underrun error interrupt\n");
+
+ if (intr & XLLF_INT_TPOE_MASK)
+ dev_err(fifo->dt_device, "transmit overrun error interrupt\n");
+
+ if (intr & XLLF_INT_TSE_MASK)
+ dev_err(fifo->dt_device,
+ "transmit length mismatch error interrupt\n");
+
+ iowrite32(XLLF_INT_CLEAR_ALL, fifo->base_addr + XLLF_ISR_OFFSET);
return IRQ_HANDLED;
}
--
2.50.0
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