linux-kernel - Re: [PATCH v5 00/10] x86/hyperv/hv_vtl: Use a wakeup mailbox to boot secondary CPUs

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Message-ID: <20250919025928.GA9212@ranerica-svr.sc.intel.com>
Date: Thu, 18 Sep 2025 19:59:28 -0700
From: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
To: x86@...nel.org, Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, Rob Herring <robh@...nel.org>,
	"K. Y. Srinivasan" <kys@...rosoft.com>,
	Haiyang Zhang <haiyangz@...rosoft.com>,
	Wei Liu <wei.liu@...nel.org>, Dexuan Cui <decui@...rosoft.com>,
	Michael Kelley <mhklinux@...look.com>,
	"Rafael J. Wysocki" <rafael@...nel.org>
Cc: Saurabh Sengar <ssengar@...ux.microsoft.com>,
	Chris Oo <cho@...rosoft.com>,
	"Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
	linux-hyperv@...r.kernel.org, devicetree@...r.kernel.org,
	linux-acpi@...r.kernel.org, linux-kernel@...r.kernel.org,
	Ricardo Neri <ricardo.neri@...el.com>,
	Yunhong Jiang <yunhong.jiang@...ux.intel.com>,
	Thomas Gleixner <tglx@...utronix.de>
Subject: Re: [PATCH v5 00/10] x86/hyperv/hv_vtl: Use a wakeup mailbox to boot
 secondary CPUs

On Wed, Aug 20, 2025 at 04:11:35PM -0700, Ricardo Neri wrote:
> On Fri, Jun 27, 2025 at 08:35:06PM -0700, Ricardo Neri wrote:
> > Hi,
> > 
> > Here is a new version of this series. Thanks to Rafael for his feedback!
> > I incorporated his feedback in this updated version. Please see the
> > changelog for details.
> > 
> > If the DeviceTree bindings look good, then the patches should be ready for
> > review by the x86, ACPI, and Hyper-V maintainers.
> > 
> > I did not change the cover letter but I included it here for completeness.
> > 
> > Thanks in advance for your feedback!
> 
> Hello,
> 
> I would like to know what else is needed to move this patchset forward.
> Rafael and Rob have reviewed the DeviceTree bindings. Rafael has reviewed
> the relocation of the code that makes use of the mailbox.
> 
> Would it be possible for the Hyper-V maintainers to take a look (Michael
> Kelley has reviewed the patches already)? Perhaps this could increase the
> confidence of the x86 maintainers.

Many thanks Dexuan for reviewing this series. Now that the relevant
subsystem maintainers have reviewed their portions of the series, perhaps
the x86 maintainers could take a look?

Thanks in advance!

BR,
Ricardo