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Message-ID: <2718480.Icojqenx9y@senjougahara>
Date: Fri, 19 Sep 2025 15:29:46 +0900
From: Mikko Perttunen <mperttunen@...dia.com>
To: Thierry Reding <thierry.reding@...il.com>,
Thierry Reding <treding@...dia.com>, Jonathan Hunter <jonathanh@...dia.com>,
Sowjanya Komatineni <skomatineni@...dia.com>,
Luca Ceresoli <luca.ceresoli@...tlin.com>, David Airlie <airlied@...il.com>,
Simona Vetter <simona@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Prashant Gaikwad <pgaikwad@...dia.com>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Svyatoslav Ryhel <clamor95@...il.com>, Dmitry Osipenko <digetx@...il.com>,
Jonas Schwöbel <jonasschwoebel@...oo.de>,
Charan Pedumuru <charan.pedumuru@...il.com>,
Svyatoslav Ryhel <clamor95@...il.com>
Cc: dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-media@...r.kernel.org, linux-clk@...r.kernel.org,
linux-staging@...ts.linux.dev
Subject:
Re: [PATCH v2 01/23] clk: tegra: set CSUS as vi_sensors gate for Tegra20,
Tegra30 and Tegra114
On Saturday, September 6, 2025 10:53 PM Svyatoslav Ryhel wrote:
> CSUS clock which is camera MCLK, is also a clock gate for vi_sensor so
> lets model it by creating CSUS grate with vi_sensor as a parent.
s/grate/gate/; "vi_sensor's" in commit message.
The commit message is a bit difficult to understand (to me at least), perhaps explain it in terms of the clock signal flow, e.g. "The CSUS clock is a clock gate for the output clock signal primarily sourced from the VI_SENSOR clock. This clock signal is used as an input MCLK clock for cameras."
For Tegra30/114, I think this is correct. For Tegra20, I noticed that for the two other output clocks -- cdev1 and cdev2 -- we already are modelling the source clock muxing in the clock framework through clocks called cdev1_mux and cdev2_mux which are registered as read-only mux clocks in pinctrl-tegra20.c. So I think the same should be done for csus -- add a csus_mux clock in pinctrl-tegra20.c, and make it csus's parent. For Tegra30 and later chips, these output clocks seem to have only one source clock.
Thanks,
Mikko
>
> Signed-off-by: Svyatoslav Ryhel <clamor95@...il.com>
> ---
> drivers/clk/tegra/clk-tegra114.c | 7 ++++++-
> drivers/clk/tegra/clk-tegra20.c | 7 ++++++-
> drivers/clk/tegra/clk-tegra30.c | 7 ++++++-
> 3 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> index 186b0b81c1ec..00282b0d3763 100644
> --- a/drivers/clk/tegra/clk-tegra114.c
> +++ b/drivers/clk/tegra/clk-tegra114.c
> @@ -691,7 +691,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
> [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
> [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
> [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
> - [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true },
> [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true },
> [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true },
> [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true },
> @@ -1047,6 +1046,12 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
> 0, 82, periph_clk_enb_refcnt);
> clks[TEGRA114_CLK_DSIB] = clk;
>
> + /* csus */
> + clk = tegra_clk_register_periph_gate("csus", "vi_sensor", 0,
> + clk_base, 0, TEGRA114_CLK_CSUS,
> + periph_clk_enb_refcnt);
> + clks[TEGRA114_CLK_CSUS] = clk;
> +
> /* emc mux */
> clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
> ARRAY_SIZE(mux_pllmcp_clkm),
> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
> index 2c58ce25af75..bf9a9f8ddf62 100644
> --- a/drivers/clk/tegra/clk-tegra20.c
> +++ b/drivers/clk/tegra/clk-tegra20.c
> @@ -530,7 +530,6 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
> [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true },
> [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true },
> [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true },
> - [tegra_clk_csus] = { .dt_id = TEGRA20_CLK_CSUS, .present = true },
> [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true },
> [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true },
> [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true },
> @@ -807,6 +806,12 @@ static void __init tegra20_periph_clk_init(void)
> clk_register_clkdev(clk, NULL, "dsi");
> clks[TEGRA20_CLK_DSI] = clk;
>
> + /* csus */
> + clk = tegra_clk_register_periph_gate("csus", "vi_sensor", 0,
> + clk_base, 0, TEGRA20_CLK_CSUS,
> + periph_clk_enb_refcnt);
> + clks[TEGRA20_CLK_CSUS] = clk;
> +
> /* pex */
> clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,
> periph_clk_enb_refcnt);
> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
> index 82a8cb9545eb..ca367184e185 100644
> --- a/drivers/clk/tegra/clk-tegra30.c
> +++ b/drivers/clk/tegra/clk-tegra30.c
> @@ -779,7 +779,6 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
> [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },
> [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },
> [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true },
> - [tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true },
> [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true },
> [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true },
> [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true },
> @@ -1008,6 +1007,12 @@ static void __init tegra30_periph_clk_init(void)
> 0, 48, periph_clk_enb_refcnt);
> clks[TEGRA30_CLK_DSIA] = clk;
>
> + /* csus */
> + clk = tegra_clk_register_periph_gate("csus", "vi_sensor", 0,
> + clk_base, 0, TEGRA30_CLK_CSUS,
> + periph_clk_enb_refcnt);
> + clks[TEGRA30_CLK_CSUS] = clk;
> +
> /* pcie */
> clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
> 70, periph_clk_enb_refcnt);
>
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