Message-ID: <20250919093119.24d2711a@erd003.prtnl>
Date: Fri, 19 Sep 2025 09:31:19 +0200
From: David Jander <david@...tonic.nl>
To: Oleksij Rempel <o.rempel@...gutronix.de>
Cc: Andrew Lunn <andrew@...n.ch>, Jonas Rebmann <jre@...gutronix.de>,
 Vladimir Oltean <olteanv@...il.com>, "David S. Miller"
 <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski
 <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Rob Herring
 <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Liam Girdwood <lgirdwood@...il.com>, Mark Brown
 <broonie@...nel.org>, Shengjiu Wang <shengjiu.wang@....com>, Shawn Guo
 <shawnguo@...nel.org>, Sascha Hauer <s.hauer@...gutronix.de>, Fabio Estevam
 <festevam@...il.com>, Pengutronix Kernel Team <kernel@...gutronix.de>,
 Vladimir Oltean <vladimir.oltean@....com>, netdev@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-sound@...r.kernel.org, imx@...ts.linux.dev,
 linux-arm-kernel@...ts.infradead.org, Lucas Stach <l.stach@...gutronix.de>
Subject: Re: [PATCH v2 3/3] arm64: dts: add Protonic PRT8ML board

On Fri, 19 Sep 2025 07:08:45 +0200
Oleksij Rempel <o.rempel@...gutronix.de> wrote:

> On Thu, Sep 18, 2025 at 05:33:47PM +0200, David Jander wrote:
> > On Thu, 18 Sep 2025 17:04:55 +0200
> > Andrew Lunn <andrew@...n.ch> wrote:
> >   
> > > > Yes, unfortunately the SJA1105Q does not support PAUSE frames, and the i.MX8MP
> > > > FEC isn't able to sustain 1000Mbps (only about 400ish) due to insufficient
> > > > internal bus bandwidth. It will generate PAUSE frames, but the SJA1105Q
> > > > ignores these, leading to packet loss, which is obviously worse than
> > > > restricting this link to 100Mbps. Ironically both chips are from the same
> > > > manufacturer, yet are incompatible in this regard.    
> > > 
> > > Thanks for the explanation. Maybe add a comment that the bandwidth is
> > > limited due to the lack of flow control resulting in packet loss in
> > > the FEC.
> > >
> > > Anything which looks odd deserves a comment, otherwise somebody will
> > > question it....  
> > 
> > Yes! This is a golden tip. Ironically what I said above is incorrect. Sorry
> > for the noise.
> > 
> > Ftr: I wrote this DT about 4 years ago, so my memory failed me, and a comment
> > in the code would have saved me this embarrassment ;-)
> > 
> > The comment above applies to the i.MX6 SoC's which had this limitation. On the
> > i.MX8MP we had a different problem that also caused the SJA1105Q not to work
> > reliably at 1000Mbps either. We haven't been able to find the issue, but so far
> > this switch hasn't been able to work at 1000Mbps reliable on any platform,
> > possibly for different reasons in each case.  
> 
> May be it is doe to RGMII clock switching issue and the requirement to
> have specific silence time for proper clock frequency detection on the
> switch side?

I doubt it is that, because it works well at 100Mbps still in RGMII mode, and
according to the documentation the delay line is active for all rates.

OTOH, this switch probably has some other issues related to the RXC delay
line. It is always the RX path (RX at the switch, TX at the MAC) that
randomly does not work.

OT (but still posting in case someone here knows something):
Coincidentally I am currently working on a different design with a SJA1105Q
switch connected to a LAN743X MAC. The complication is that this MAC cannot
disable the TXC (RXC at the switch) at all. Still working on this, but right
now it looks like not even with the RX delay line deactivated (doing the delay
at the MAC) is the switch working reliably (at 1000Mbps). Investigation still
on-going so take with grain of salt.

> Or it is just artifact from iMX6 platform and it should be retested?

I remember having tested it and it not working reliably, but that was 4 years
ago or so. Drivers have evolved since, so maybe it is worth testing again?

Best regards,

-- 
David Jander

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