linux-kernel - Re: [PATCH v2 3/4] arm64: dts: imx8mm-evk: limit the max frequency of spi nor chip

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Message-ID: <20250919093034.GK9196@nxa18884-linux.ap.freescale.net>
Date: Fri, 19 Sep 2025 17:30:34 +0800
From: Peng Fan <peng.fan@....nxp.com>
To: Michael Walle <michael@...le.cc>
Cc: Haibo Chen <haibo.chen@....com>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Pengutronix Kernel Team <kernel@...gutronix.de>,
	Fabio Estevam <festevam@...il.com>, Peng Fan <peng.fan@....com>,
	Frank Li <frank.li@....com>, Marco Felsch <m.felsch@...gutronix.de>,
	Han Xu <han.xu@....com>, devicetree@...r.kernel.org,
	imx@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 3/4] arm64: dts: imx8mm-evk: limit the max frequency
 of spi nor chip

On Fri, Sep 19, 2025 at 09:29:41AM +0200, Michael Walle wrote:
>Hi,
>
>On Thu Sep 18, 2025 at 11:01 AM CEST, Peng Fan wrote:
>> On Wed, Sep 17, 2025 at 04:42:29PM +0800, Haibo Chen wrote:
>> >The spi nor on imx8mm evk board works under SDR mode, and
>> >driver use FlexSPIn_MCR0[RXCLKSRC] = 0x0 for SDR mode.
>> >According to the datasheet, there is IO limitation on this chip,
>> >the max frequency of such case is 66MHz, so add the limitation
>> >here to align with datasheet.
>> >
>> >Refer to 3.9.10 FlexSPI timing parameters on page 59.
>> >https://www.nxp.com/docs/en/data-sheet/IMX8MMIEC.pdf
>>
>> The SoC SDR mode max supports 66MHz, 133MHz. DDR mode max supports 33MHz and
>> 66MHz. Saying the driver now only use RXCLKSRC 0 to restrict the
>> device tree to 66MHz is not that correct.
>>
>> The SoC max frequency could be coded in driver per my understanding.
>
>Yes that is correct. The spi-max-frequency property is for the
>device, not the capabilities of the controller. I.e. the flash chip
>on the board.
>
>> For the QSPI-NOR chip, the spi-max-frequency should represent the NOR chip
>> frequency. But that chip supports SDR/DDR, so a new property
>> spi-ddr-max-frequency, if we take spi-max-frequency as the max NOR
>> CHIP SDR mode frequency?
>
>Which chip is it? I'm not sure that this is required because the
>supported modes might be in the SFDP data and we just support the
>8d8d8d mode backed by the JEDEC standard.

MT25QU256ABA
Clock frequency
– 166 MHz (MAX) for all protocols in STR
– 90 MHz (MAX) for all protocols in DTR

Current spi-max-frequency does not indicate it is STR or DDR.

If device tree has spi-max-frequency as 166MHz, but driver configures
the working mode as DDR, there might be issues. I not look into details
on SFDP or 8d8d8d8d, so my understandings might be wrong.

Thanks,
Peng

>
>-michael
>
>> So if spi-max-frequency is the maximum NOR chip SDR frequency, the driver
>> should also be update dthat DDR mode is not supported as of now.
>>
>> Just my thoughts.
>>
>> Regards
>> Peng.
>