linux-kernel - [PATCH v1 0/3] Workarounds and optimizations for Neoverse-V3AE

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Message-ID: <20250919145832.4035534-1-ryan.roberts@arm.com>
Date: Fri, 19 Sep 2025 15:58:27 +0100
From: Ryan Roberts <ryan.roberts@....com>
To: Catalin Marinas <catalin.marinas@....com>,
	Will Deacon <will@...nel.org>,
	Mark Rutland <mark.rutland@....com>,
	James Morse <james.morse@....com>
Cc: Ryan Roberts <ryan.roberts@....com>,
	linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Subject: [PATCH v1 0/3] Workarounds and optimizations for Neoverse-V3AE

Hi All,

I know it's late in the cycle, but I thought I'd try my luck at sneaking this
in.

Neoverse-V3AE has a different MIDR value to Neoverse-V3, but qualifies for the
same workarounds and optimizations ("SSBS not fully self-synchronizing" and
BBML2_NOABORT) so this just adds Neoverse-V3AE wherever Neoverse-V3 appears.
Details in the commits.

The last patch adds Neoverse-3VAE to the BBML2_NOABORT allow list. That will
conflict with the patch you have already queued to add AmpereOne, and with the
patch you said you would do to remove X4. But this is a one-liner so trivial to
resolve.

Applies on v6.17-rc5.

Thanks,
Ryan

Mark Rutland (2):
  arm64: cputype: Add Neoverse-V3AE definitions
  arm64: errata: Apply workarounds for Neoverse-V3AE

Ryan Roberts (1):
  arm64: cpufeature: add Neoverse-V3AE to BBML2 allow list

 Documentation/arch/arm64/silicon-errata.rst | 2 ++
 arch/arm64/Kconfig                          | 1 +
 arch/arm64/include/asm/cputype.h            | 2 ++
 arch/arm64/kernel/cpu_errata.c              | 1 +
 arch/arm64/kernel/cpufeature.c              | 1 +
 5 files changed, 7 insertions(+)

--
2.43.0