linux-kernel - Re: [PATCH 1/2] arm64: dts: rockchip: correct uart mux for Radxa ZERO 3

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <07560892-6672-45a0-aa3d-79e47d145ff4@kwiboo.se>
Date: Sat, 20 Sep 2025 10:14:45 +0200
From: Jonas Karlman <jonas@...boo.se>
To: Ed Wildgoose <lists@...dgooses.com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, Heiko Stuebner <heiko@...ech.de>,
 "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
 "linux-arm-kernel@...ts.infradead.org"
 <linux-arm-kernel@...ts.infradead.org>,
 "linux-rockchip@...ts.infradead.org" <linux-rockchip@...ts.infradead.org>,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/2] arm64: dts: rockchip: correct uart mux for Radxa ZERO
 3

Hi Ed,

On 9/17/2025 1:49 PM, Ed Wildgoose wrote:
> The rk3566 has multiplexed pins and the uarts can be moved to a choice
> of 2 pin groups. The default rk356x-base.dtsi appears to default to mux0
> for all uarts, however, specific hardware might choose to implement
> alternatives
> 
> The Radxa zero 3 shows that is uses M1 for uarts:
> - uart4
> - uart5
> - uart9
> 
> These aren't normally enabled, but we should at least correct the
> default pinctrl definitions. Without these changes there will be
> conflicts with mmc0/mmc1, leading to the SD or eMMC going missing.

Please rephrase the commit subject and message, currently it seem to
imply that there is something broken that needs fixing, however this
mainly make it easier to apply an overlay that does not include
description of any changed behavior for pins on the 40-pin header.

Current expected behavior of the hw, using pins on 40-pin header as gpio
pins should already be correctly described in this board device tree.

My original intent when submitting board device trees, such as this one, 
is that a device tree overlay will fully describe any required changes.
Also I do not expect that using an overlay intended for an old vendor
kernel device tree will work as-is on mainline kernel device tree.

> 
> Signed-off-by: Ed Wildgoose <lists@...dgooses.com>
> ---
>  .../boot/dts/rockchip/rk3566-radxa-zero-3.dtsi    | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
> index 1ee5d96a4..41b3c4403 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
> @@ -492,6 +492,21 @@ &uart2 {
>  	status = "okay";
>  };
>  
> +&uart4{

nit: missing space

> +    pinctrl-names = "default";
> +    pinctrl-0 = <&uart4m1_xfer>;

nit: seem to use space instead of tab, same for rest.

Regards,
Jonas

> +};
> +
> +&uart5 {
> +    pinctrl-names = "default";
> +    pinctrl-0 = <&uart5m1_xfer>;
> +};
> +
> +&uart9 {
> +    pinctrl-names = "default";
> +    pinctrl-0 = <&uart9m1_xfer>;
> +};
> +
>  &usb_host0_xhci {
>  	status = "okay";
>  };