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Message-ID: <mbei72eoq4vss4enwfp2c74756xdhyvd7bwfomgehm4fneardc@dgmofkbof3ie>
Date: Sat, 20 Sep 2025 18:28:35 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Wesley Cheng <wesley.cheng@....qualcomm.com>
Cc: krzk+dt@...nel.org, conor+dt@...nel.org, kishon@...nel.org,
vkoul@...nel.org, gregkh@...uxfoundation.org, robh@...nel.org,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-usb@...r.kernel.org,
linux-phy@...ts.infradead.org,
Elson Roy Serrao <quic_eserrao@...cinc.com>
Subject: Re: [PATCH 5/9] phy: qualcomm: Update the QMP clamp register for V6
On Fri, Sep 19, 2025 at 08:21:04PM -0700, Wesley Cheng wrote:
> From: Elson Roy Serrao <quic_eserrao@...cinc.com>
>
> QMP combo phy V6 and above use the clamp register from the PCS always on
> (AON) address space. Update the driver accordingly.
>
> Signed-off-by: Elson Roy Serrao <quic_eserrao@...cinc.com>
> Signed-off-by: Wesley Cheng <wesley.cheng@....qualcomm.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 38 ++++++++++++++++---
> .../phy/qualcomm/phy-qcom-qmp-pcs-aon-v6.h | 12 ++++++
> .../phy/qualcomm/phy-qcom-qmp-pcs-misc-v5.h | 12 ++++++
> 3 files changed, 57 insertions(+), 5 deletions(-)
> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v6.h
> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v5.h
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
--
With best wishes
Dmitry
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