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Message-Id: <20250920-mt6582-v1-4-b887720f577d@protonmail.com>
Date: Sat, 20 Sep 2025 20:23:29 +0200
From: Cristian Cozzolino via B4 Relay <devnull+cristian_ci.protonmail.com@...nel.org>
To: Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
Russell King <linux@...linux.org.uk>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Sean Wang <sean.wang@...iatek.com>
Cc: linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, devicetree@...r.kernel.org,
phone-devel@...r.kernel.org,
Cristian Cozzolino <cristian_ci@...tonmail.com>
Subject: [PATCH 04/10] ARM: dts: mediatek: mt6582: sort nodes and
properties
From: Cristian Cozzolino <cristian_ci@...tonmail.com>
Sort fixed clocks nodes by clock frequency and memory mapped device
nodes by reg address. Also, sort properties as shown in dt-bindings
examples.
Signed-off-by: Cristian Cozzolino <cristian_ci@...tonmail.com>
---
arch/arm/boot/dts/mediatek/mt6582.dtsi | 46 +++++++++++++++-------------------
1 file changed, 20 insertions(+), 26 deletions(-)
diff --git a/arch/arm/boot/dts/mediatek/mt6582.dtsi b/arch/arm/boot/dts/mediatek/mt6582.dtsi
index 37d2b8786188aecb65c0a6e0d31aabc3b66e2bd7..8ada8c6518661509ebee647367064187f4376ab9 100644
--- a/arch/arm/boot/dts/mediatek/mt6582.dtsi
+++ b/arch/arm/boot/dts/mediatek/mt6582.dtsi
@@ -13,8 +13,8 @@ / {
interrupt-parent = <&sysirq>;
cpus {
- #address-cells = <1>;
#size-cells = <0>;
+ #address-cells = <1>;
cpu@0 {
device_type = "cpu";
@@ -38,22 +38,22 @@ cpu@3 {
};
};
- system_clk: dummy13m {
+ uart_clk: dummy26m {
compatible = "fixed-clock";
- clock-frequency = <13000000>;
#clock-cells = <0>;
+ clock-frequency = <26000000>;
};
- rtc_clk: dummy32k {
+ system_clk: dummy13m {
compatible = "fixed-clock";
- clock-frequency = <32000>;
#clock-cells = <0>;
+ clock-frequency = <13000000>;
};
- uart_clk: dummy26m {
+ rtc_clk: dummy32k {
compatible = "fixed-clock";
- clock-frequency = <26000000>;
#clock-cells = <0>;
+ clock-frequency = <32000>;
};
soc {
@@ -62,6 +62,11 @@ soc {
compatible = "simple-bus";
ranges;
+ watchdog: watchdog@...07000 {
+ compatible = "mediatek,mt6582-wdt", "mediatek,mt6589-wdt";
+ reg = <0x10007000 0x100>;
+ };
+
timer: timer@...08000 {
compatible = "mediatek,mt6577-timer";
reg = <0x10008000 0x80>;
@@ -71,18 +76,17 @@ timer: timer@...08000 {
};
sysirq: interrupt-controller@...00100 {
- compatible = "mediatek,mt6582-sysirq",
- "mediatek,mt6577-sysirq";
+ compatible = "mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq";
+ reg = <0x10200100 0x1c>;
+ interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <3>;
- interrupt-parent = <&gic>;
- reg = <0x10200100 0x1c>;
};
gic: interrupt-controller@...11000 {
compatible = "arm,cortex-a7-gic";
- interrupt-controller;
#interrupt-cells = <3>;
+ interrupt-controller;
interrupt-parent = <&gic>;
reg = <0x10211000 0x1000>,
<0x10212000 0x2000>,
@@ -91,8 +95,7 @@ gic: interrupt-controller@...11000 {
};
uart0: serial@...02000 {
- compatible = "mediatek,mt6582-uart",
- "mediatek,mt6577-uart";
+ compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart";
reg = <0x11002000 0x400>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
@@ -100,8 +103,7 @@ uart0: serial@...02000 {
};
uart1: serial@...03000 {
- compatible = "mediatek,mt6582-uart",
- "mediatek,mt6577-uart";
+ compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart";
reg = <0x11003000 0x400>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
@@ -109,8 +111,7 @@ uart1: serial@...03000 {
};
uart2: serial@...04000 {
- compatible = "mediatek,mt6582-uart",
- "mediatek,mt6577-uart";
+ compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart";
reg = <0x11004000 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
@@ -118,18 +119,11 @@ uart2: serial@...04000 {
};
uart3: serial@...05000 {
- compatible = "mediatek,mt6582-uart",
- "mediatek,mt6577-uart";
+ compatible = "mediatek,mt6582-uart", "mediatek,mt6577-uart";
reg = <0x11005000 0x400>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
clocks = <&uart_clk>;
status = "disabled";
};
-
- watchdog: watchdog@...07000 {
- compatible = "mediatek,mt6582-wdt",
- "mediatek,mt6589-wdt";
- reg = <0x10007000 0x100>;
- };
};
};
--
2.49.0
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