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Message-Id: <20250921005300.2535994-5-anshuman.khandual@arm.com> Date: Sun, 21 Sep 2025 06:23:00 +0530 From: Anshuman Khandual <anshuman.khandual@....com> To: linux-arm-kernel@...ts.infradead.org, will@...nel.org Cc: Anshuman Khandual <anshuman.khandual@....com>, Catalin Marinas <catalin.marinas@....com>, Marc Zyngier <maz@...nel.org>, Oliver Upton <oliver.upton@...ux.dev>, Mark Brown <broonie@...nel.org>, Ryan Roberts <ryan.roberts@....com>, kvmarm@...ts.linux.dev, linux-kernel@...r.kernel.org Subject: [PATCH V5 4/4] KVM: arm64: Move inside all required TCR_XXX macros Move all required TCR_XXX macros into KVM header (asm/kvm_arm.h) for their continued usage in KVM. Cc: Catalin Marinas <catalin.marinas@....com> Cc: Will Deacon <will@...nel.org> Cc: Marc Zyngier <maz@...nel.org> Cc: Mark Brown <broonie@...nel.org> Cc: kvmarm@...ts.linux.dev Cc: linux-arm-kernel@...ts.infradead.org Cc: linux-kernel@...r.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@....com> --- arch/arm64/include/asm/kvm_arm.h | 43 ++++++++++++++++++++++++++ arch/arm64/include/asm/pgtable-hwdef.h | 43 -------------------------- 2 files changed, 43 insertions(+), 43 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 1da290aeedce..236e828c69cc 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -107,6 +107,49 @@ #define MPAMHCR_HOST_FLAGS 0 +#define TCR_T0SZ_MASK TCR_EL1_T0SZ_MASK +#define TCR_T1SZ_MASK TCR_EL1_T1SZ_MASK + +#define TCR_EPD0_MASK TCR_EL1_EPD0_MASK +#define TCR_EPD1_MASK TCR_EL1_EPD1_MASK + +#define TCR_IRGN0_MASK TCR_EL1_IRGN0_MASK +#define TCR_IRGN0_WBWA (TCR_EL1_IRGN0_WBWA << TCR_EL1_IRGN0_SHIFT) + +#define TCR_ORGN0_MASK TCR_EL1_ORGN0_MASK +#define TCR_ORGN0_WBWA (TCR_EL1_ORGN0_WBWA << TCR_EL1_ORGN0_SHIFT) + +#define TCR_SH0_MASK TCR_EL1_SH0_MASK +#define TCR_SH0_INNER (TCR_EL1_SH0_INNER << TCR_EL1_SH0_SHIFT) + +#define TCR_TG0_SHIFT TCR_EL1_TG0_SHIFT +#define TCR_TG0_MASK TCR_EL1_TG0_MASK +#define TCR_TG0_4K (TCR_EL1_TG0_4K << TCR_EL1_TG0_SHIFT) +#define TCR_TG0_64K (TCR_EL1_TG0_64K << TCR_EL1_TG0_SHIFT) +#define TCR_TG0_16K (TCR_EL1_TG0_16K << TCR_EL1_TG0_SHIFT) + +#define TCR_TG1_SHIFT TCR_EL1_TG1_SHIFT +#define TCR_TG1_MASK TCR_EL1_TG1_MASK +#define TCR_TG1_16K (TCR_EL1_TG1_16K << TCR_EL1_TG1_SHIFT) +#define TCR_TG1_4K (TCR_EL1_TG1_4K << TCR_EL1_TG1_SHIFT) +#define TCR_TG1_64K (TCR_EL1_TG1_64K << TCR_EL1_TG1_SHIFT) + +#define TCR_IPS_SHIFT TCR_EL1_IPS_SHIFT +#define TCR_IPS_MASK TCR_EL1_IPS_MASK +#define TCR_A1 TCR_EL1_A1 +#define TCR_ASID16 TCR_EL1_AS +#define TCR_TBI0 TCR_EL1_TBI0 +#define TCR_TBI1 TCR_EL1_TBI1 +#define TCR_HA TCR_EL1_HA +#define TCR_HD TCR_EL1_HD +#define TCR_HPD0 TCR_EL1_HPD0 +#define TCR_HPD1 TCR_EL1_HPD1 +#define TCR_TBID0 TCR_EL1_TBID0 +#define TCR_TBID1 TCR_EL1_TBID1 +#define TCR_E0PD0 TCR_EL1_E0PD0 +#define TCR_E0PD1 TCR_EL1_E0PD1 +#define TCR_DS TCR_EL1_DS + /* TCR_EL2 Registers bits */ #define TCR_EL2_DS (1UL << 32) #define TCR_EL2_RES1 ((1U << 31) | (1 << 23)) diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h index 2c0ba17ed1a3..5059abda78d8 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -231,49 +231,6 @@ #define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_EL1_T0SZ_SHIFT) #define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_EL1_T1SZ_SHIFT) -#define TCR_T0SZ_MASK TCR_EL1_T0SZ_MASK -#define TCR_T1SZ_MASK TCR_EL1_T1SZ_MASK - -#define TCR_EPD0_MASK TCR_EL1_EPD0_MASK -#define TCR_EPD1_MASK TCR_EL1_EPD1_MASK - -#define TCR_IRGN0_MASK TCR_EL1_IRGN0_MASK -#define TCR_IRGN0_WBWA (TCR_EL1_IRGN0_WBWA << TCR_EL1_IRGN0_SHIFT) - -#define TCR_ORGN0_MASK TCR_EL1_ORGN0_MASK -#define TCR_ORGN0_WBWA (TCR_EL1_ORGN0_WBWA << TCR_EL1_ORGN0_SHIFT) - -#define TCR_SH0_MASK TCR_EL1_SH0_MASK -#define TCR_SH0_INNER (TCR_EL1_SH0_INNER << TCR_EL1_SH0_SHIFT) - -#define TCR_TG0_SHIFT TCR_EL1_TG0_SHIFT -#define TCR_TG0_MASK TCR_EL1_TG0_MASK -#define TCR_TG0_4K (TCR_EL1_TG0_4K << TCR_EL1_TG0_SHIFT) -#define TCR_TG0_64K (TCR_EL1_TG0_64K << TCR_EL1_TG0_SHIFT) -#define TCR_TG0_16K (TCR_EL1_TG0_16K << TCR_EL1_TG0_SHIFT) - -#define TCR_TG1_SHIFT TCR_EL1_TG1_SHIFT -#define TCR_TG1_MASK TCR_EL1_TG1_MASK -#define TCR_TG1_16K (TCR_EL1_TG1_16K << TCR_EL1_TG1_SHIFT) -#define TCR_TG1_4K (TCR_EL1_TG1_4K << TCR_EL1_TG1_SHIFT) -#define TCR_TG1_64K (TCR_EL1_TG1_64K << TCR_EL1_TG1_SHIFT) - -#define TCR_IPS_SHIFT TCR_EL1_IPS_SHIFT -#define TCR_IPS_MASK TCR_EL1_IPS_MASK -#define TCR_A1 TCR_EL1_A1 -#define TCR_ASID16 TCR_EL1_AS -#define TCR_TBI0 TCR_EL1_TBI0 -#define TCR_TBI1 TCR_EL1_TBI1 -#define TCR_HA TCR_EL1_HA -#define TCR_HD TCR_EL1_HD -#define TCR_HPD0 TCR_EL1_HPD0 -#define TCR_HPD1 TCR_EL1_HPD1 -#define TCR_TBID0 TCR_EL1_TBID0 -#define TCR_TBID1 TCR_EL1_TBID1 -#define TCR_E0PD0 TCR_EL1_E0PD0 -#define TCR_E0PD1 TCR_EL1_E0PD1 -#define TCR_DS TCR_EL1_DS - /* * TTBR. */ -- 2.25.1
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