linux-kernel - Re: [PATCH v2] arm64/mm: Elide TLB flush in certain pte protection transitions

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Message-ID: <d84eef92-115e-4b71-9146-86fc91244c15@arm.com>
Date: Sun, 21 Sep 2025 17:53:30 +0530
From: Anshuman Khandual <anshuman.khandual@....com>
To: Dev Jain <dev.jain@....com>, catalin.marinas@....com, will@...nel.org
Cc: wangkefeng.wang@...wei.com, ryan.roberts@....com, baohua@...nel.org,
 pjaroszynski@...dia.com, linux-arm-kernel@...ts.infradead.org,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] arm64/mm: Elide TLB flush in certain pte protection
 transitions

On 20/09/25 10:40 AM, Dev Jain wrote:
> Currently arm64 does an unconditional TLB flush in mprotect(). This is not
> required for some cases, for example, when changing from PROT_NONE to
> PROT_READ | PROT_WRITE (a real usecase - glibc malloc does this to emulate

The following transition does not require a TLB flush on all
architectures ? In which case, should not this check be part
of generic mprotect() itself.

PROT_NONE ---> PROT_READ | PROT_WRITE
> growing into the non-main heaps), and unsetting uffd-wp in a range.
> 
> Therefore, implement pte_needs_flush() for arm64, which is already
> implemented by some other arches as well.

Agreed, defining pte_needs_flush() on the platform does make
sense, if it brings some perf improvement without additional
cost.
> 
> Running a userspace program changing permissions back and forth between
> PROT_NONE and PROT_READ | PROT_WRITE, and measuring the average time taken
> for the none->rw transition, I get a reduction from 3.2 microseconds to
> 2.85 microseconds, giving a 12.3% improvement.

But that's a very specific workload intended to demonstrate
the use case for this change. Hence the improvement claimed
here is not representative of real world work loads.
> 
> Reviewed-by: Kefeng Wang <wangkefeng.wang@...wei.com>
> Signed-off-by: Dev Jain <dev.jain@....com>
> ---
> mm-selftests pass.
> 
> v1->v2:
>  - Drop PTE_PRESENT_INVALID and PTE_AF checks, use ptdesc_t instead of
>    pteval_t, return !!diff (Ryan)
> 
>  arch/arm64/include/asm/tlbflush.h | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index 18a5dc0c9a54..40df783ba09a 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -524,6 +524,33 @@ static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *b
>  {
>  	__flush_tlb_range_nosync(mm, start, end, PAGE_SIZE, true, 3);
>  }
> +
> +static inline bool __pte_flags_need_flush(ptdesc_t oldval, ptdesc_t newval)
> +{
> +	ptdesc_t diff = oldval ^ newval;
> +
> +	/* invalid to valid transition requires no flush */
> +	if (!(oldval & PTE_VALID))
> +		return false;

Is not this true for all platforms which could be checked via
pte_present() helper ? Hence should not this be moved inside
the caller itself in generic MM ? I guess probably the above
mentioned transition should be moved as well.

PROT_NONE ---> PROT_READ | PROT_WRITE
> +
> +	/* Transition in the SW bits requires no flush */
> +	diff &= ~PTE_SWBITS_MASK;
> +
> +	return !!diff;
> +}
> +
> +static inline bool pte_needs_flush(pte_t oldpte, pte_t newpte)
> +{
> +	return __pte_flags_need_flush(pte_val(oldpte), pte_val(newpte));
> +}
> +#define pte_needs_flush pte_needs_flush
> +
> +static inline bool huge_pmd_needs_flush(pmd_t oldpmd, pmd_t newpmd)
> +{
> +	return __pte_flags_need_flush(pmd_val(oldpmd), pmd_val(newpmd));
> +}
> +#define huge_pmd_needs_flush huge_pmd_needs_flush
> +
>  #endif
>  
>  #endif