linux-kernel - [PATCH v2 4/5] ARM: dts: qcom: msm8960: add I2C nodes for gsbi1 and gsbi8

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Message-Id: <20250921-msm8960-reorder-v2-4-26c478366d21@smankusors.com>
Date: Sun, 21 Sep 2025 03:08:12 +0000 (UTC)
From: Antony Kurniawan Soemardi <linux@...nkusors.com>
To: Bjorn Andersson <andersson@...nel.org>, 
 Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org, 
 linux-kernel@...r.kernel.org, 
 Antony Kurniawan Soemardi <linux@...nkusors.com>, 
 David Heidelberg <david@...t.cz>, Max Shevchenko <wctrl@...ton.me>, 
 Rudraksha Gupta <guptarud@...il.com>, Shinjo Park <peremen@...il.com>
Subject: [PATCH v2 4/5] ARM: dts: qcom: msm8960: add I2C nodes for gsbi1
 and gsbi8

These are present on msm8960 and are required for devices such as the
Casio G'zOne, which has NFC wired to gsbi1 and audio amplifier wired to
gsbi8.

The nodes are added disabled by default.

Co-developed-by: Shinjo Park <peremen@...il.com>
Signed-off-by: Shinjo Park <peremen@...il.com>
Signed-off-by: Antony Kurniawan Soemardi <linux@...nkusors.com>
---
 arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 70 ++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
index 890b34bdf8c3376659570218500e28ce5809c26a..0aaf60dcda647dc2f7ce11ae7cde05a0bcd35716 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
@@ -131,6 +131,24 @@ msmgpio: pinctrl@...000 {
 			interrupt-controller;
 			#interrupt-cells = <2>;
 
+			i2c1_default_state: i2c1-default-state {
+				i2c1-pins {
+					pins = "gpio8", "gpio9";
+					function = "gsbi1";
+					drive-strength = <8>;
+					bias-disable;
+				};
+			};
+
+			i2c1_sleep_state: i2c1-sleep-state {
+				i2c1-pins {
+					pins = "gpio8", "gpio9";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-bus-hold;
+				};
+			};
+
 			i2c3_default_state: i2c3-default-state {
 				i2c3-pins {
 					pins = "gpio16", "gpio17";
@@ -149,6 +167,24 @@ i2c3-pins {
 				};
 			};
 
+			i2c8_default_state: i2c8-default-state {
+				i2c8-pins {
+					pins = "gpio36", "gpio37";
+					function = "gsbi8";
+					drive-strength = <8>;
+					bias-disable;
+				};
+			};
+
+			i2c8_sleep_state: i2c8-sleep-state {
+				i2c8-pins {
+					pins = "gpio36", "gpio37";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-bus-hold;
+				};
+			};
+
 			i2c10_default_state: i2c10-default-state {
 				i2c10-pins {
 					pins = "gpio73", "gpio74";
@@ -474,6 +510,23 @@ gsbi1: gsbi@...00000 {
 
 			status = "disabled";
 
+			gsbi1_i2c: i2c@...80000 {
+				compatible = "qcom,i2c-qup-v1.1.1";
+				reg = <0x16080000 0x1000>;
+				pinctrl-0 = <&i2c1_default_state>;
+				pinctrl-1 = <&i2c1_sleep_state>;
+				pinctrl-names = "default", "sleep";
+				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GSBI1_QUP_CLK>,
+					 <&gcc GSBI1_H_CLK>;
+				clock-names = "core",
+					      "iface";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+
 			gsbi1_spi: spi@...80000 {
 				compatible = "qcom,spi-qup-v1.1.1";
 				reg = <0x16080000 0x1000>;
@@ -572,6 +625,23 @@ gsbi8_serial: serial@...40000 {
 
 				status = "disabled";
 			};
+
+			gsbi8_i2c: i2c@...80000 {
+				compatible = "qcom,i2c-qup-v1.1.1";
+				reg = <0x1a080000 0x1000>;
+				pinctrl-0 = <&i2c8_default_state>;
+				pinctrl-1 = <&i2c8_sleep_state>;
+				pinctrl-names = "default", "sleep";
+				interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gcc GSBI8_QUP_CLK>,
+					 <&gcc GSBI8_H_CLK>;
+				clock-names = "core",
+					      "iface";
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
 		};
 
 		gsbi10: gsbi@...00000 {

-- 
2.34.1