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Message-ID: <t4x7okzjvh5ltyoniwlreoyy76735igtnxpeohpbojn4hkqk4q@v3ayfjrkez3e>
Date: Tue, 23 Sep 2025 02:39:49 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Rob Clark <rob.clark@....qualcomm.com>
Cc: Xiangxu Yin <xiangxu.yin@....qualcomm.com>, Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Dmitry Baryshkov <lumag@...nel.org>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Jessica Zhang <jessica.zhang@....qualcomm.com>,
Sean Paul <sean@...rly.run>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
fange.zhang@....qualcomm.com, yongxing.mou@....qualcomm.com,
li.liu@....qualcomm.com, Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>
Subject: Re: [PATCH v5 14/14] drm/msm/dp: Add support for lane mapping
configuration
On Mon, Sep 22, 2025 at 08:13:00AM -0700, Rob Clark wrote:
> On Fri, Sep 19, 2025 at 11:35 AM Dmitry Baryshkov
> <dmitry.baryshkov@....qualcomm.com> wrote:
> >
> > On Fri, Sep 19, 2025 at 10:24:31PM +0800, Xiangxu Yin wrote:
> > > QCS615 platform requires non-default logical-to-physical lane mapping due
> > > to its unique hardware routing. Unlike the standard mapping sequence
> > > <0 1 2 3>, QCS615 uses <3 2 0 1>, which necessitates explicit
> > > configuration via the data-lanes property in the device tree. This ensures
> > > correct signal routing between the DP controller and PHY.
> > >
> > > For partial definitions, fill remaining lanes with unused physical lanes
> > > in ascending order.
> > >
> > > Signed-off-by: Xiangxu Yin <xiangxu.yin@....qualcomm.com>
> > > ---
> > > drivers/gpu/drm/msm/dp/dp_ctrl.c | 10 +++----
> > > drivers/gpu/drm/msm/dp/dp_link.c | 60 ++++++++++++++++++++++++++++++++++++++++
> > > drivers/gpu/drm/msm/dp/dp_link.h | 1 +
> > > 3 files changed, 66 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_link.c
> > > index 2aeb3ecf76fab2ee6a9512b785ca5dceebfc3964..34a91e194a124ef5372f13352f7b3513aa88da2a 100644
> > > --- a/drivers/gpu/drm/msm/dp/dp_link.c
> > > +++ b/drivers/gpu/drm/msm/dp/dp_link.c
> > > @@ -1236,6 +1236,61 @@ static u32 msm_dp_link_link_frequencies(struct device_node *of_node)
> > > return frequency;
> > > }
> > >
> > > +/*
> > > + * Always populate msm_dp_link->lane_map with 4 lanes.
> > > + * - Use DTS "data-lanes" if present; otherwise fall back to default mapping.
> > > + * - For partial definitions, fill remaining entries with unused lanes in
> > > + * ascending order.
> > > + */
> > > +static int msm_dp_link_lane_map(struct device *dev, struct msm_dp_link *msm_dp_link)
> > > +{
> > > + struct device_node *of_node = dev->of_node;
> > > + struct device_node *endpoint;
> > > + int cnt = msm_dp_link->max_dp_lanes;
> > > + u32 tmp[DP_MAX_NUM_DP_LANES];
> > > + u32 map[DP_MAX_NUM_DP_LANES] = {0, 1, 2, 3}; /* default 1:1 mapping */
> > > + bool used[DP_MAX_NUM_DP_LANES] = {false};
> > > + int i, j = 0, ret = -EINVAL;
> > > +
> > > + endpoint = of_graph_get_endpoint_by_regs(of_node, 1, -1);
> > > + if (endpoint) {
> > > + ret = of_property_read_u32_array(endpoint, "data-lanes", tmp, cnt);
> > > + if (ret)
> > > + dev_dbg(dev, "endpoint data-lanes read failed (ret=%d)\n", ret);
> > > + }
> > > +
> > > + if (ret) {
> > > + ret = of_property_read_u32_array(of_node, "data-lanes", tmp, cnt);
> > > + if (ret) {
> > > + dev_info(dev, "data-lanes not defined, set to default\n");
> > > + goto out;
> > > + }
> > > + }
> > > +
> > > + for (i = 0; i < cnt; i++) {
> > > + if (tmp[i] >= DP_MAX_NUM_DP_LANES) {
> > > + dev_err(dev, "data-lanes[%d]=%u out of range\n", i, tmp[i]);
> > > + return -EINVAL;
> > > + }
> > > + used[tmp[i]] = true;
> > > + map[i] = tmp[i];
> > > + }
> > > +
> > > + /* Fill the remaining entries with unused physical lanes (ascending) */
> > > + for (i = cnt; i < DP_MAX_NUM_DP_LANES && j < DP_MAX_NUM_DP_LANES; j++) {
> >
> > Nit: i = cnt, j = 0; Don't init loop variables at the top of the
> > function.
>
> These days we can party like it's c99 and declare loop variables
> inside the for(), instead of at the top of the function. My
> preference is to do so, unless the loop variable is used after the
> loop.
Ack, works for me too. I think I'm not used for having theese parts of
C99 allowed in the kernel.
--
With best wishes
Dmitry
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