linux-kernel - Re: [PATCH v2 18/23] staging: media: tegra-video: tegra20: increase maximum VI clock frequency

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Message-ID: <CAPVz0n2AjRPMuZbLAnc=9TriPHDLOFok+Qz3zoSpQSKX1R=cqg@mail.gmail.com>
Date: Mon, 22 Sep 2025 07:58:28 +0300
From: Svyatoslav Ryhel <clamor95@...il.com>
To: Mikko Perttunen <mperttunen@...dia.com>
Cc: Thierry Reding <thierry.reding@...il.com>, Thierry Reding <treding@...dia.com>, 
	Jonathan Hunter <jonathanh@...dia.com>, Sowjanya Komatineni <skomatineni@...dia.com>, 
	Luca Ceresoli <luca.ceresoli@...tlin.com>, David Airlie <airlied@...il.com>, 
	Simona Vetter <simona@...ll.ch>, Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, 
	Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Prashant Gaikwad <pgaikwad@...dia.com>, Michael Turquette <mturquette@...libre.com>, 
	Stephen Boyd <sboyd@...nel.org>, Mauro Carvalho Chehab <mchehab@...nel.org>, 
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Dmitry Osipenko <digetx@...il.com>, 
	Jonas Schwöbel <jonasschwoebel@...oo.de>, 
	Charan Pedumuru <charan.pedumuru@...il.com>, dri-devel@...ts.freedesktop.org, 
	devicetree@...r.kernel.org, linux-tegra@...r.kernel.org, 
	linux-kernel@...r.kernel.org, linux-media@...r.kernel.org, 
	linux-clk@...r.kernel.org, linux-staging@...ts.linux.dev
Subject: Re: [PATCH v2 18/23] staging: media: tegra-video: tegra20: increase
 maximum VI clock frequency

пн, 22 вер. 2025 р. о 07:54 Mikko Perttunen <mperttunen@...dia.com> пише:
>
> On Saturday, September 6, 2025 10:53 PM Svyatoslav Ryhel wrote:
> > Increase maximum VI clock frequency to 450MHz to allow correct work with
> > high resolution camera sensors.
> >
> > Signed-off-by: Svyatoslav Ryhel <clamor95@...il.com>
> > ---
> >  drivers/staging/media/tegra-video/tegra20.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/media/tegra-video/tegra20.c
> > index e0da496bb50f..3c5bafebfcd8 100644
> > --- a/drivers/staging/media/tegra-video/tegra20.c
> > +++ b/drivers/staging/media/tegra-video/tegra20.c
> > @@ -590,7 +590,7 @@ const struct tegra_vi_soc tegra20_vi_soc = {
> >       .ops = &tegra20_vi_ops,
> >       .hw_revision = 1,
> >       .vi_max_channels = 2, /* TEGRA_VI_OUT_1 and TEGRA_VI_OUT_2 */
> > -     .vi_max_clk_hz = 150000000,
> > +     .vi_max_clk_hz = 450000000,
> >       .has_h_v_flip = true,
> >  };
> >
> >
>
> Where does the 450MHz come from? Instead of hardcoding this value for each SoC, could we just clk_set_rate(ULONG_MAX) like e.g. the vic driver does, or does that get a too high rate?
>

This values comes from downstream 3.1 tegra30 sources and setting it
higher breaks VI, I have tried. If it is set lower (150MHz as it was)
it breaks VI for cameras with resolution higher then 2MP

>