linux-kernel - linux-next: manual merge of the kvm-x86 tree with the tip tree

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Message-ID: <aNEb7o3xrTDQ6JP4@finisterre.sirena.org.uk>
Date: Mon, 22 Sep 2025 10:50:38 +0100
From: Mark Brown <broonie@...nel.org>
To: Sean Christopherson <seanjc@...gle.com>
Cc: Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	Linux Next Mailing List <linux-next@...r.kernel.org>,
	Peter Zijlstra <peterz@...radead.org>
Subject: linux-next: manual merge of the kvm-x86 tree with the tip tree

Hi all,

Today's linux-next merge of the kvm-x86 tree got a conflict in:

  arch/x86/kvm/emulate.c

between commit:

  6204aea36b74c ("KVM: x86: Introduce EM_ASM_1")

from the tip tree and commit:

  f8457615b71c6 ("KVM: x86: Don't emulate instructions affected by CET features")

from the kvm-x86 tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

diff --cc arch/x86/kvm/emulate.c
index 796d0c64f9baf,5c5fb6a6f7f92..0000000000000
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@@ -4001,11 -4153,11 +4088,11 @@@ static const struct opcode group4[] = 
  };
  
  static const struct opcode group5[] = {
 -	F(DstMem | SrcNone | Lock,		em_inc),
 -	F(DstMem | SrcNone | Lock,		em_dec),
 +	I(DstMem | SrcNone | Lock,		em_inc),
 +	I(DstMem | SrcNone | Lock,		em_dec),
- 	I(SrcMem | NearBranch | IsBranch,       em_call_near_abs),
- 	I(SrcMemFAddr | ImplicitOps | IsBranch, em_call_far),
+ 	I(SrcMem | NearBranch | IsBranch | ShadowStack, em_call_near_abs),
+ 	I(SrcMemFAddr | ImplicitOps | IsBranch | ShadowStack, em_call_far),
 -	I(SrcMem | NearBranch | IsBranch, em_jmp_abs),
 +	I(SrcMem | NearBranch | IsBranch,       em_jmp_abs),
  	I(SrcMemFAddr | ImplicitOps | IsBranch, em_jmp_far),
  	I(SrcMem | Stack | TwoMemOp,		em_push), D(Undefined),
  };
diff --cc arch/x86/include/asm/cpufeatures.h
index b2a562217d3ff,8738bd783de22..0000000000000
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@@ -495,8 -496,7 +496,9 @@@
  #define X86_FEATURE_TSA_SQ_NO		(21*32+11) /* AMD CPU not vulnerable to TSA-SQ */
  #define X86_FEATURE_TSA_L1_NO		(21*32+12) /* AMD CPU not vulnerable to TSA-L1 */
  #define X86_FEATURE_CLEAR_CPU_BUF_VM	(21*32+13) /* Clear CPU buffers using VERW before VMRUN */
 -#define X86_FEATURE_MSR_IMM		(21*32+14) /* MSR immediate form instructions */
 +#define X86_FEATURE_IBPB_EXIT_TO_USER	(21*32+14) /* Use IBPB on exit-to-userspace, see VMSCAPE bug */
 +#define X86_FEATURE_ABMC		(21*32+15) /* Assignable Bandwidth Monitoring Counters */
++#define X86_FEATURE_MSR_IMM		(21*32+16) /* MSR immediate form instructions */
  
  /*
   * BUG word(s)
diff --cc arch/x86/include/asm/msr-index.h
index 718a55d82fe45,717baeba6db3c..0000000000000
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@@ -315,14 -315,15 +315,16 @@@
  #define PERF_CAP_PT_IDX			16
  
  #define MSR_PEBS_LD_LAT_THRESHOLD	0x000003f6
 -
+ #define PERF_CAP_LBR_FMT		0x3f
  #define PERF_CAP_PEBS_TRAP		BIT_ULL(6)
  #define PERF_CAP_ARCH_REG		BIT_ULL(7)
  #define PERF_CAP_PEBS_FORMAT		0xf00
+ #define PERF_CAP_FW_WRITES		BIT_ULL(13)
  #define PERF_CAP_PEBS_BASELINE		BIT_ULL(14)
 +#define PERF_CAP_PEBS_TIMING_INFO	BIT_ULL(17)
  #define PERF_CAP_PEBS_MASK		(PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
 -					 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE)
 +					 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \
 +					 PERF_CAP_PEBS_TIMING_INFO)
  
  #define MSR_IA32_RTIT_CTL		0x00000570
  #define RTIT_CTL_TRACEEN		BIT(0)
diff --cc arch/x86/kvm/emulate.c
index 796d0c64f9baf,5c5fb6a6f7f92..0000000000000
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@@ -4001,11 -4153,11 +4088,11 @@@ static const struct opcode group4[] = 
  };
  
  static const struct opcode group5[] = {
  	F(DstMem | SrcNone | Lock,		em_inc),
  	F(DstMem | SrcNone | Lock,		em_dec),
- 	I(SrcMem | NearBranch | IsBranch,       em_call_near_abs),
- 	I(SrcMemFAddr | ImplicitOps | IsBranch, em_call_far),
+ 	I(SrcMem | NearBranch | IsBranch | ShadowStack, em_call_near_abs),
+ 	I(SrcMemFAddr | ImplicitOps | IsBranch | ShadowStack, em_call_far),
 -	I(SrcMem | NearBranch | IsBranch, em_jmp_abs),
 +	I(SrcMem | NearBranch | IsBranch,       em_jmp_abs),
  	I(SrcMemFAddr | ImplicitOps | IsBranch, em_jmp_far),
  	I(SrcMem | Stack | TwoMemOp,		em_push), D(Undefined),
  };

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