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Message-ID: <371a8b2a-1e89-4735-b8cd-5c00643e9ab6@collabora.com>
Date: Mon, 22 Sep 2025 11:58:23 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Daniel Golle <daniel@...rotopia.org>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd
<sboyd@...nel.org>, Matthias Brugger <matthias.bgg@...il.com>,
Uwe Kleine-König <u.kleine-koenig@...libre.com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Sam Shih <sam.shih@...iatek.com>, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org
Subject: Re: [PATCH RESEND] clk: mediatek: mt7988-infracfg: SPI0 clocks are
not critical
Il 21/09/25 19:58, Daniel Golle ha scritto:
> SPI0 clocks have wrongly been marked as critical while, probably due
> to the SPI driver not requesting them. This can (and should) be addressed
> in device tree instead.
> Remove CLK_IS_CRITICAL flag from clocks related to SPI0.
>
Eh, technically you're right about the Fixes tag - but if there is a problem in the
devicetree and this patch gets backported to older releases, the device gets broken
in all old kernels.
So - I agree with this change and besides, the SPI clocks are correctly declared in
at least mt7988a.dtsi so I don't see this breaking any device in the current kernel
but please, at this point, drop the Fixes tag so that we avoid backports.
Once the tag is removed, you can add my
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Cheers,
Angelo
> Fixes: 4b4719437d85 ("clk: mediatek: add drivers for MT7988 SoC")
> Signed-off-by: Daniel Golle <daniel@...rotopia.org>
> ---
> Patch originally sent 2024-10-31 but never received any feedback.
>
> drivers/clk/mediatek/clk-mt7988-infracfg.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mt7988-infracfg.c b/drivers/clk/mediatek/clk-mt7988-infracfg.c
> index ef8267319d91..c40e18c27f12 100644
> --- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
> +++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
> @@ -196,12 +196,10 @@ static const struct mtk_gate infra_clks[] = {
> GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
> GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", "sysaxi_sel", 11,
> CLK_IS_CRITICAL),
> - GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12,
> - CLK_IS_CRITICAL),
> + GATE_INFRA2(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", "infra_mux_spi0_sel", 12),
> GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", "infra_mux_spi1_sel", 13),
> GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", "infra_mux_spi2_sel", 14),
> - GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15,
> - CLK_IS_CRITICAL),
> + GATE_INFRA2(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", "sysaxi_sel", 15),
> GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", "sysaxi_sel", 16),
> GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", "sysaxi_sel", 17),
> GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", "sysaxi_sel", 18),
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