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Message-Id: <20250922-dr1v90-basic-dt-v2-2-64d28500cb37@pigmoral.tech>
Date: Mon, 22 Sep 2025 20:46:32 +0800
From: Junhui Liu <junhui.liu@...moral.tech>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>, Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Samuel Holland <samuel.holland@...ive.com>,
Anup Patel <anup@...infault.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>, Junhui Liu <junhui.liu@...moral.tech>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Palmer Dabbelt <palmer@...ive.com>, Conor Dooley <conor@...nel.org>,
linux-riscv@...ts.infradead.org, linux-serial@...r.kernel.org
Subject: [PATCH v2 02/11] dt-bindings: riscv: Add Nuclei UX900 compatibles
The UX900 is a RISC-V core from Nuclei, used in the Anlogic DR1V90 SoC.
It features a 64-bit architecture and dual-issue, 9-stage pipeline, with
lots of optional extensions including V, K, Zc, and more.
Signed-off-by: Junhui Liu <junhui.liu@...moral.tech>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 1a0cf0702a45d2df38c48f50d66b3d2ac3715da5..cd3299490380696fff54a41355c6ecbc75316047 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -48,6 +48,7 @@ properties:
- amd,mbv64
- andestech,ax45mp
- canaan,k210
+ - nuclei,ux900
- sifive,bullet0
- sifive,e5
- sifive,e7
--
2.51.0
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