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Message-Id: <20250922-dr1v90-basic-dt-v2-7-64d28500cb37@pigmoral.tech>
Date: Mon, 22 Sep 2025 20:46:37 +0800
From: Junhui Liu <junhui.liu@...moral.tech>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>, Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Samuel Holland <samuel.holland@...ive.com>,
Anup Patel <anup@...infault.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>, Junhui Liu <junhui.liu@...moral.tech>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Palmer Dabbelt <palmer@...ive.com>, Conor Dooley <conor@...nel.org>,
linux-riscv@...ts.infradead.org, linux-serial@...r.kernel.org
Subject: [PATCH v2 07/11] riscv: Add Anlogic SoC famly Kconfig support
The first SoC in the Anlogic series is DR1V90, which contains a RISC-V
core from Nuclei.
Signed-off-by: Junhui Liu <junhui.liu@...moral.tech>
---
arch/riscv/Kconfig.socs | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 61ceae0aa27a6fa3a91da6a46becfd96da99fd09..c1c0681f4364647477c50518725d9323922ff270 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -7,6 +7,11 @@ config ARCH_ANDES
help
This enables support for Andes SoC platform hardware.
+config ARCH_ANLOGIC
+ bool "Anlogic SoCs"
+ help
+ This enables support for Anlogic SoC platform hardware.
+
config ARCH_MICROCHIP_POLARFIRE
def_bool ARCH_MICROCHIP
--
2.51.0
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