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Message-Id: <20250922-dr1v90-basic-dt-v2-11-64d28500cb37@pigmoral.tech>
Date: Mon, 22 Sep 2025 20:46:41 +0800
From: Junhui Liu <junhui.liu@...moral.tech>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, 
 Paul Walmsley <paul.walmsley@...ive.com>, 
 Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
 Alexandre Ghiti <alex@...ti.fr>, Daniel Lezcano <daniel.lezcano@...aro.org>, 
 Thomas Gleixner <tglx@...utronix.de>, 
 Samuel Holland <samuel.holland@...ive.com>, 
 Anup Patel <anup@...infault.org>, 
 Greg Kroah-Hartman <gregkh@...uxfoundation.org>, 
 Jiri Slaby <jirislaby@...nel.org>, Junhui Liu <junhui.liu@...moral.tech>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
 Palmer Dabbelt <palmer@...ive.com>, Conor Dooley <conor@...nel.org>, 
 linux-riscv@...ts.infradead.org, linux-serial@...r.kernel.org
Subject: [PATCH v2 11/11] MAINTAINERS: Setup support for Anlogic DR1V90 SoC
 tree

Add myself as the maintainer of the Anlogic DR1V90 SoC tree, including
the corresponding DTS and DT bindings paths for Anlogic RISC-V-based
SoCs.

Signed-off-by: Junhui Liu <junhui.liu@...moral.tech>
---
 MAINTAINERS | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 520fb4e379a3954ff9b163bfdfda857e5c5b99d4..44b4b4f7e53c5904f6b9076f9542866292d33fce 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21681,6 +21681,15 @@ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux.git
 F:	Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
 F:	drivers/iommu/riscv/
 
+RISC-V ANLOGIC DR1V90 SoC SUPPORT
+M:	Junhui Liu <junhui.liu@...moral.tech>
+L:	linux-riscv@...ts.infradead.org
+S:	Maintained
+T:	git https://github.com/pigmoral/linux-dr1v90
+F:	Documentation/devicetree/bindings/riscv/anlogic.yaml
+F:	arch/riscv/boot/dts/anlogic/
+N:	dr1v90
+
 RISC-V MICROCHIP FPGA SUPPORT
 M:	Conor Dooley <conor.dooley@...rochip.com>
 M:	Daire McNamara <daire.mcnamara@...rochip.com>

-- 
2.51.0


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