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Message-ID: <CAMRc=Mf9OB03FXEpSXG8XeJhtd7MkwJTH=rY11SBb9SazCMqJw@mail.gmail.com>
Date: Mon, 22 Sep 2025 16:22:14 +0200
From: Bartosz Golaszewski <brgl@...ev.pl>
To: "Herve Codina (Schneider Electric)" <herve.codina@...tlin.com>
Cc: Thomas Gleixner <tglx@...utronix.de>, Wolfram Sang <wsa+renesas@...g-engineering.com>,
Hoan Tran <hoan@...amperecomputing.com>, Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>, Magnus Damm <magnus.damm@...il.com>,
Saravana Kannan <saravanak@...gle.com>, Serge Semin <fancer.lancer@...il.com>,
Phil Edworthy <phil.edworthy@...esas.com>, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-renesas-soc@...r.kernel.org, Pascal Eberhard <pascal.eberhard@...com>,
Miquel Raynal <miquel.raynal@...tlin.com>, Thomas Petazzoni <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH v3 5/8] ARM: dts: r9a06g032: Add GPIO controllers
On Thu, Sep 18, 2025 at 12:40 PM Herve Codina (Schneider Electric)
<herve.codina@...tlin.com> wrote:
>
> Add GPIO controllers (Synosys DesignWare IPs) available in the
> r9a06g032 (RZ/N1D) SoC.
>
> Signed-off-by: Herve Codina (Schneider Electric) <herve.codina@...tlin.com>
> Reviewed-by: Wolfram Sang <wsa+renesas@...g-engineering.com>
> Tested-by: Wolfram Sang <wsa+renesas@...g-engineering.com>
> ---
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
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