linux-kernel - [PATCH 0/5] clk/reset: anlogic: add support for DR1V90 SoC

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Message-Id: <20250922-dr1v90-cru-v1-0-e393d758de4e@pigmoral.tech>
Date: Mon, 22 Sep 2025 22:51:46 +0800
From: Junhui Liu <junhui.liu@...moral.tech>
To: Michael Turquette <mturquette@...libre.com>, 
 Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, Junhui Liu <junhui.liu@...moral.tech>, 
 Philipp Zabel <p.zabel@...gutronix.de>, 
 Paul Walmsley <paul.walmsley@...ive.com>, 
 Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
 Alexandre Ghiti <alex@...ti.fr>
Cc: linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org, 
 devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org, 
 "fushan.zeng" <fushan.zeng@...ogic.com>
Subject: [PATCH 0/5] clk/reset: anlogic: add support for DR1V90 SoC

This patch series adds Clock and Reset Unit (CRU) support for the
Anlogic DR1V90 SoC, as well as corresponding dts bindings and dts
integration.

The CRU driver framework is built around the clock controller as the
primary device, with the reset controller implemented as an auxiliary
device.

The Anlogic DR1 series includes not only the DR1V90 (based on the Nuclei
UX900 RISC-V core), but also the DR1M90 (based on the Cortex-A35 ARM64
core). Most of the clock tree and CRU design can be shared between them.
This series only adds CRU support for DR1V90. Nevertheless, the driver
is structured to make future extension to other DR1 variants like
DR1M90.

This depends on the basic dt series for DR1V90 SoC [1].

Link: https://lore.kernel.org/all/20250922-dr1v90-basic-dt-v2-0-64d28500cb37@pigmoral.tech/ [1]

---
Junhui Liu (5):
      clk: correct clk_div_mask() return value for width == 32
      dt-bindings: clock: add Anlogic DR1V90 CRU
      clk: anlogic: add cru support for Anlogic DR1V90 SoC
      reset: anlogic: add support for Anlogic DR1V90 resets
      riscv: dts: anlogic: add clocks and CRU for DR1V90

 .../bindings/clock/anlogic,dr1v90-cru.yaml         |  60 +++++
 arch/riscv/boot/dts/anlogic/dr1v90.dtsi            |  41 +++-
 drivers/clk/Kconfig                                |   1 +
 drivers/clk/Makefile                               |   1 +
 drivers/clk/anlogic/Kconfig                        |   9 +
 drivers/clk/anlogic/Makefile                       |   5 +
 drivers/clk/anlogic/cru-dr1v90.c                   | 190 +++++++++++++++
 drivers/clk/anlogic/cru_dr1.c                      | 258 +++++++++++++++++++++
 drivers/clk/anlogic/cru_dr1.h                      | 117 ++++++++++
 drivers/reset/Kconfig                              |   9 +
 drivers/reset/Makefile                             |   1 +
 drivers/reset/reset-dr1v90.c                       | 136 +++++++++++
 include/dt-bindings/clock/anlogic,dr1v90-cru.h     |  46 ++++
 include/dt-bindings/reset/anlogic,dr1v90-cru.h     |  42 ++++
 include/linux/clk-provider.h                       |   2 +-
 15 files changed, 915 insertions(+), 3 deletions(-)
---
base-commit: 02fc12d7c5a58a010fe2bfaedbc0a5b3cc1cc231
change-id: 20250922-dr1v90-cru-74ab40c7f273
prerequisite-message-id: <20250922-dr1v90-basic-dt-v2-0-64d28500cb37@...moral.tech>
prerequisite-patch-id: dc2c18c600b0efd0e3237c11b580cb011b3f5070
prerequisite-patch-id: d67ae8ee7c8f7dcb35dc7417d002b1d9cb4d928d
prerequisite-patch-id: ab3aa9ae32dee038edbee3fd0c809fe4bb724d1c
prerequisite-patch-id: 376f134b341ff8ad728dbb094808eec7f74f95f5
prerequisite-patch-id: 3ab69aeadf1aba02977276bc21488d7599bfe1d5
prerequisite-patch-id: 2c6db06e8d61a46fbd68f6ecc49e111ad0e5f145
prerequisite-patch-id: f19a96b19ab1cdd9f71843e46e7ded542aee1607
prerequisite-patch-id: fa4c88d32c053108b28c6f567b563ad29870a881
prerequisite-patch-id: f2d425237bac7c99e29a7e6c47a1e6362986b923
prerequisite-patch-id: 72df5f2d85ee2234887ad66d38be3dff51439346
prerequisite-patch-id: b8e5a06023a0d521946b6df41713f26d189d66b7

Best regards,
-- 
Junhui Liu <junhui.liu@...moral.tech>