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Message-ID: <2797545.mvXUDI8C0e@jernej-laptop>
Date: Tue, 23 Sep 2025 16:22:26 +0200
From: Jernej Škrabec <jernej.skrabec@...il.com>
To: Andrew Lunn <andrew+netdev@...n.ch>,
"David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej@...nel.org>, Samuel Holland <samuel@...lland.org>,
Chen-Yu Tsai <wens@...nel.org>
Cc: netdev@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-sunxi@...ts.linux.dev,
linux-kernel@...r.kernel.org, Andre Przywara <andre.przywara@....com>
Subject:
Re: [PATCH net-next v7 2/6] net: stmmac: Add support for Allwinner A523
GMAC200
Dne torek, 23. september 2025 ob 16:02:42 Srednjeevropski poletni čas je Chen-Yu Tsai napisal(a):
> From: Chen-Yu Tsai <wens@...e.org>
>
> The Allwinner A523 SoC family has a second Ethernet controller, called
> the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for
> numbering. This controller, according to BSP sources, is fully
> compatible with a slightly newer version of the Synopsys DWMAC core.
> The glue layer around the controller is the same as found around older
> DWMAC cores on Allwinner SoCs. The only slight difference is that since
> this is the second controller on the SoC, the register for the clock
> delay controls is at a different offset. Last, the integration includes
> a dedicated clock gate for the memory bus and the whole thing is put in
> a separately controllable power domain.
>
> Add a new driver for this hardware supporting the integration layer.
>
> Signed-off-by: Chen-Yu Tsai <wens@...e.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@...il.com>
Best regards,
Jernej
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