linux-kernel - Re: [PATCH v16 45/51] KVM: selftests: Add an MSR test to exercise guest/host and read/write

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Message-ID: <aNLQJu-1YZ7GYybw@google.com>
Date: Tue, 23 Sep 2025 09:51:50 -0700
From: Sean Christopherson <seanjc@...gle.com>
To: Chao Gao <chao.gao@...el.com>
Cc: Paolo Bonzini <pbonzini@...hat.com>, kvm@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Tom Lendacky <thomas.lendacky@....com>, Mathias Krause <minipli@...ecurity.net>, 
	John Allen <john.allen@....com>, Rick Edgecombe <rick.p.edgecombe@...el.com>, 
	Binbin Wu <binbin.wu@...ux.intel.com>, Xiaoyao Li <xiaoyao.li@...el.com>, 
	Maxim Levitsky <mlevitsk@...hat.com>, Zhang Yi Z <yi.z.zhang@...ux.intel.com>, Xin Li <xin@...or.com>
Subject: Re: [PATCH v16 45/51] KVM: selftests: Add an MSR test to exercise
 guest/host and read/write

On Tue, Sep 23, 2025, Chao Gao wrote:
> On Fri, Sep 19, 2025 at 03:32:52PM -0700, Sean Christopherson wrote:
> >+		/*
> >+		 * TSC_AUX is supported if RDTSCP *or* RDPID is supported.  Add
> >+		 * entries for each features so that TSC_AUX doesn't exists for
> >+		 * the "unsupported" vCPU, and obviously to test both cases.
> >+		 */
> >+		MSR_TEST2(MSR_TSC_AUX, 0x12345678, canonical_val, RDTSCP, RDPID),
> >+		MSR_TEST2(MSR_TSC_AUX, 0x12345678, canonical_val, RDPID, RDTSCP),
> 
> At first glance, it's unclear to me why canonical_val is invalid for
> MSR_TSC_AUX, especially since it is valid for a few other MSRs in this
> test. Should we add a note to the above comment? e.g.,
> 
> canonical_val is invalid for MSR_TSC_AUX because its high 32 bits must be 0.

Yeah, I was being lazy.  To-be-tested, but I'll squash this:

diff --git a/tools/testing/selftests/kvm/x86/msrs_test.c b/tools/testing/selftests/kvm/x86/msrs_test.c
index 9285cf51ef75..345a39030a0a 100644
--- a/tools/testing/selftests/kvm/x86/msrs_test.c
+++ b/tools/testing/selftests/kvm/x86/msrs_test.c
@@ -48,6 +48,13 @@ struct kvm_msr {
  */
 static const u64 canonical_val = 0x123456789000ull;
 
+/*
+ * Arbitrary value with bits set in every byte, but not all bits set.  This is
+ * also a non-canonical value, but that's coincidental (any 64-bit value with
+ * an alternating 0s/1s pattern will be non-canonical).
+ */
+static const u64 u64_val = 0xaaaa5555aaaa5555ull;
+
 #define MSR_TEST_CANONICAL(msr, feat)                                  \
        __MSR_TEST(msr, #msr, canonical_val, NONCANONICAL, 0, feat)
 
@@ -247,8 +254,8 @@ static void test_msrs(void)
                 * entries for each features so that TSC_AUX doesn't exists for
                 * the "unsupported" vCPU, and obviously to test both cases.
                 */
-               MSR_TEST2(MSR_TSC_AUX, 0x12345678, canonical_val, RDTSCP, RDPID),
-               MSR_TEST2(MSR_TSC_AUX, 0x12345678, canonical_val, RDPID, RDTSCP),
+               MSR_TEST2(MSR_TSC_AUX, 0x12345678, u64_val, RDTSCP, RDPID),
+               MSR_TEST2(MSR_TSC_AUX, 0x12345678, u64_val, RDPID, RDTSCP),
 
                MSR_TEST(MSR_IA32_SYSENTER_CS, 0x1234, 0, NONE),
                /*