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Message-ID: <BE3EEC385331D80D+aNHt7_J7uUMzkhrq@LT-Guozexi>
Date: Tue, 23 Sep 2025 08:46:39 +0800
From: Troy Mitchell <troy.mitchell@...ux.spacemit.com>
To: Troy Mitchell <troy.mitchell@...ux.spacemit.com>,
Andi Shyti <andi.shyti@...nel.org>, Yixun Lan <dlan@...too.org>,
Alex Elder <elder@...cstar.com>,
Troy Mitchell <troymitchell988@...il.com>,
linux-i2c@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, spacemit@...ts.linux.dev
Subject: Re: [PATCH 3/6] i2c: spacemit: disable SDA glitch fix to avoid
restart delay
On Mon, Sep 22, 2025 at 10:56:00PM +0200, Aurelien Jarno wrote:
> On 2025-08-27 15:39, Troy Mitchell wrote:
> > The K1 I2C controller has an SDA glitch fix that introduces a small
> > delay on restart signals. While this feature can suppress glitches
> > on SDA when SCL = 0, it also delays the restart signal, which may
> > cause unexpected behavior in some transfers.
> >
> > The glitch itself does not affect normal I2C operation, because
> > the I2C specification allows SDA to change while SCL is low.
> >
> > To ensure correct transmission for every message, we disable the
> > SDA glitch fix by setting the RCR.SDA_GLITCH_NOFIX bit during
> > initialization.
> >
> > This guarantees that restarts are issued promptly without
> > unintended delays.
> >
> > Fixes: 5ea558473fa31 ("i2c: spacemit: add support for SpacemiT K1 SoC")
> > Signed-off-by: Troy Mitchell <troy.mitchell@...ux.spacemit.com>
> > ---
> > drivers/i2c/busses/i2c-k1.c | 11 +++++++++++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c
> > index d342752030d077953adf84a2886211de96e843c4..c1656b78f1681729ccc2ebca6e290259d14889d9 100644
> > --- a/drivers/i2c/busses/i2c-k1.c
> > +++ b/drivers/i2c/busses/i2c-k1.c
> > @@ -14,6 +14,7 @@
> > #define SPACEMIT_ICR 0x0 /* Control register */
> > #define SPACEMIT_ISR 0x4 /* Status register */
> > #define SPACEMIT_IDBR 0xc /* Data buffer register */
> > +#define SPACEMIT_IRCR 0x18 /* Reset cycle counter */
> > #define SPACEMIT_IBMR 0x1c /* Bus monitor register */
> >
> > /* SPACEMIT_ICR register fields */
> > @@ -76,6 +77,8 @@
> > SPACEMIT_SR_GCAD | SPACEMIT_SR_IRF | SPACEMIT_SR_ITE | \
> > SPACEMIT_SR_ALD)
> >
> > +#define SPACEMIT_RCR_SDA_GLITCH_NOFIX BIT(7) /* bypass the SDA glitch fix */
> > +
>
> The datasheet seems to use FIX_BYPASS instead of NOFIX, but maybe you
> have chosen the later because it's shorter.
Yes, it is shorter so I chosen that one.
>
> > /* SPACEMIT_IBMR register fields */
> > #define SPACEMIT_BMR_SDA BIT(0) /* SDA line level */
> > #define SPACEMIT_BMR_SCL BIT(1) /* SCL line level */
> > @@ -237,6 +240,14 @@ static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c)
> > val |= SPACEMIT_CR_MSDE | SPACEMIT_CR_MSDIE;
> >
> > writel(val, i2c->base + SPACEMIT_ICR);
> > +
> > + /*
> > + * The glitch fix in the K1 I2C controller introduces a delay
> > + * on restart signals, so we disable the fix here.
> > + */
> > + val = readl(i2c->base + SPACEMIT_IRCR);
> > + val |= SPACEMIT_RCR_SDA_GLITCH_NOFIX;
> > + writel(val, i2c->base + SPACEMIT_IRCR);
> > }
> >
> > static inline void
>
> I trust you on the waveform captures, with that:
Tnx!
- Troy
>
> Reviewed-by: Aurelien Jarno <aurelien@...el32.net>
>
> --
> Aurelien Jarno GPG: 4096R/1DDD8C9B
> aurelien@...el32.net http://aurel32.net
>
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