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Message-ID: <CAMRc=MdhQMR=-ayz+GfigUMVy+j1QNO3LguMoZYa5_+Es3E5Ow@mail.gmail.com>
Date: Tue, 23 Sep 2025 09:48:41 +0200
From: Bartosz Golaszewski <brgl@...ev.pl>
To: Dang Huynh <dang.huynh@...nlining.org>
Cc: Manivannan Sadhasivam <mani@...nel.org>, Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
Vinod Koul <vkoul@...nel.org>, Ulf Hansson <ulf.hansson@...aro.org>,
Philipp Zabel <p.zabel@...gutronix.de>, Kees Cook <kees@...nel.org>,
"Gustavo A. R. Silva" <gustavoars@...nel.org>, linux-arm-kernel@...ts.infradead.org,
linux-unisoc@...ts.infradead.org, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, dmaengine@...r.kernel.org,
linux-mmc@...r.kernel.org, linux-hardening@...r.kernel.org,
Conor Dooley <conor.dooley@...rochip.com>
Subject: Re: [PATCH 00/10] RDA8810PL SD/MMC support
On Tue, Sep 23, 2025 at 5:45 AM Dang Huynh <dang.huynh@...nlining.org> wrote:
>
> On Mon, Sep 22, 2025 at 04:17:05PM +0200, Bartosz Golaszewski wrote:
> > On Thu, Sep 18, 2025 at 8:49 PM Dang Huynh via B4 Relay
> > <devnull+dang.huynh.mainlining.org@...nel.org> wrote:
> > >
> > > This patch series aims to add SDMMC driver and various drivers required
> > > for SDMMC controller to function.
> > >
> > > This also fixed a bug where all the GPIO switched from INPUT to OUTPUT
> > > after the GPIO driver probed or by reading the GPIO debugfs.
> > >
> > > This patch series is a split from [1] to ease the maintainers.
> > >
> >
> > This is still targeting at least 4 subsystems and isn't making the
> > merging any easier. Are there any build-time dependencies here? If
> > not, then split it further into small chunks targeting individual
> > subsystems and the relevant ARM SoC tree.
> The MMC driver depends on both the clock and the DMA driver.
>
But is the dependency a build-time one or does the MMC DT node
reference clocks and the DMA engine by phandle? I assume it's the
latter in which case it's fine for them to go into next separately.
Bart
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