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Message-Id: <20250923084739.1281-1-dongxuyang@eswincomputing.com>
Date: Tue, 23 Sep 2025 16:47:39 +0800
From: dongxuyang@...incomputing.com
To: mturquette@...libre.com,
sboyd@...nel.org,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
linux-clk@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: ningyu@...incomputing.com,
linmin@...incomputing.com,
huangyifeng@...incomputing.com,
pinkesh.vaghela@...fochips.com,
Xuyang Dong <dongxuyang@...incomputing.com>
Subject: [PATCH v5 1/2] dt-bindings: clock: eswin: Documentation for eic7700 SoC
From: Xuyang Dong <dongxuyang@...incomputing.com>
Add device tree binding documentation for the ESWIN eic7700
clock controller module.
Signed-off-by: Yifeng Huang <huangyifeng@...incomputing.com>
Signed-off-by: Xuyang Dong <dongxuyang@...incomputing.com>
---
.../bindings/clock/eswin,eic7700-clock.yaml | 40 ++
.../dt-bindings/clock/eswin,eic7700-clock.h | 379 ++++++++++++++++++
2 files changed, 419 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
create mode 100644 include/dt-bindings/clock/eswin,eic7700-clock.h
diff --git a/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml b/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
new file mode 100644
index 000000000000..49053543ecfe
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/eswin,eic7700-clock.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/eswin,eic7700-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Eswin EIC7700 SoC clock controller
+
+maintainers:
+ - Yifeng Huang <huangyifeng@...incomputing.com>
+ - Xuyang Dong <dongxuyang@...incomputing.com>
+
+description:
+ The clock controller generates and supplies clock to all the modules
+ for eic7700 SoC.
+
+properties:
+ compatible:
+ const: eswin,eic7700-clock
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@...28000 {
+ compatible = "eswin,eic7700-clock";
+ reg = <0x51828000 0x200>;
+ #clock-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/eswin,eic7700-clock.h b/include/dt-bindings/clock/eswin,eic7700-clock.h
new file mode 100644
index 000000000000..c5cd67be3649
--- /dev/null
+++ b/include/dt-bindings/clock/eswin,eic7700-clock.h
@@ -0,0 +1,379 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2025, Beijing ESWIN Computing Technology Co.,
+ * Ltd.. All rights reserved.
+ *
+ * Device Tree binding constants for EIC7700 clock controller.
+ *
+ * Authors:
+ * Yifeng Huang <huangyifeng@...incomputing.com>
+ * Xuyang Dong <dongxuyang@...incomputing.com>
+ */
+
+#ifndef _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_
+#define _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_
+
+#define EIC7700_CLK_XTAL_24M 0
+#define EIC7700_CLK_XTAL_32K 1
+#define EIC7700_CLK_PLL_CPU 2
+#define EIC7700_CLK_SPLL0_FOUT1 3
+#define EIC7700_CLK_SPLL0_FOUT2 4
+#define EIC7700_CLK_SPLL0_FOUT3 5
+#define EIC7700_CLK_SPLL1_FOUT1 6
+#define EIC7700_CLK_SPLL1_FOUT2 7
+#define EIC7700_CLK_SPLL1_FOUT3 8
+#define EIC7700_CLK_SPLL2_FOUT1 9
+#define EIC7700_CLK_SPLL2_FOUT2 10
+#define EIC7700_CLK_SPLL2_FOUT3 11
+#define EIC7700_CLK_VPLL_FOUT1 12
+#define EIC7700_CLK_VPLL_FOUT2 13
+#define EIC7700_CLK_VPLL_FOUT3 14
+#define EIC7700_CLK_APLL_FOUT1 15
+#define EIC7700_CLK_APLL_FOUT2 16
+#define EIC7700_CLK_APLL_FOUT3 17
+#define EIC7700_CLK_EXT_MCLK 18
+#define EIC7700_CLK_PLL_DDR 19
+#define EIC7700_CLK_LPDDR_REF_BAK 20
+#define EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE 21
+#define EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE 22
+#define EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE 23
+#define EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE 24
+#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0 25
+#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1 26
+#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2 27
+#define EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE 28
+#define EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE 29
+#define EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE 30
+#define EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE 31
+#define EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE 32
+#define EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE 33
+#define EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1 34
+#define EIC7700_CLK_MUX_VO_CEC_2MUX1 35
+#define EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE 36
+#define EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE 37
+#define EIC7700_CLK_MUX_RTC_2MUX1 38
+#define EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE 39
+#define EIC7700_CLK_MUX_NOCNSP_XTAL_2MUX1 40
+#define EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE 41
+#define EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE 42
+#define EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE 43
+#define EIC7700_CLK_MUX_GPU_ACLK_XTAL_2MUX1 44
+#define EIC7700_CLK_MUX_DSP_ACLK_XTAL_2MUX1 45
+#define EIC7700_CLK_MUX_D2D_ACLK_XTAL_2MUX1 46
+#define EIC7700_CLK_MUX_HSP_ACLK_XTAL_2MUX1 47
+#define EIC7700_CLK_MUX_PCIE_ACLK_XTAL_2MUX1 48
+#define EIC7700_CLK_MUX_NPU_ACLK_XTAL_2MUX1 49
+#define EIC7700_CLK_MUX_NPU_LLC_XTAL_2MUX1 50
+#define EIC7700_CLK_MUX_NPU_CORE_XTAL_2MUX1 51
+#define EIC7700_CLK_MUX_VI_ACLK_XTAL_2MUX1 52
+#define EIC7700_CLK_MUX_VI_DVP_XTAL_2MUX1 53
+#define EIC7700_CLK_MUX_VI_DIG_ISP_XTAL_2MUX1 54
+#define EIC7700_CLK_MUX_VI_SHUTTER_XTAL_2MUX1_0 55
+#define EIC7700_CLK_MUX_VI_SHUTTER_XTAL_2MUX1_1 56
+#define EIC7700_CLK_MUX_VI_SHUTTER_XTAL_2MUX1_2 57
+#define EIC7700_CLK_MUX_VI_SHUTTER_XTAL_2MUX1_3 58
+#define EIC7700_CLK_MUX_VI_SHUTTER_XTAL_2MUX1_4 59
+#define EIC7700_CLK_MUX_VI_SHUTTER_XTAL_2MUX1_5 60
+#define EIC7700_CLK_MUX_VO_ACLK_XTAL_2MUX1 61
+#define EIC7700_CLK_MUX_IESMCLK_XTAL_2MUX1 62
+#define EIC7700_CLK_MUX_VO_PIXEL_XTAL_2MUX1 63
+#define EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK 64
+#define EIC7700_CLK_MUX_VC_ACLK_XTAL_2MUX1 65
+#define EIC7700_CLK_MUX_JD_XTAL_2MUX1 66
+#define EIC7700_CLK_MUX_JE_XTAL_2MUX1 67
+#define EIC7700_CLK_MUX_VE_XTAL_2MUX1 68
+#define EIC7700_CLK_MUX_VD_XTAL_2MUX1 69
+#define EIC7700_CLK_MUX_SATA_PHY_2MUX1 70
+#define EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE 71
+#define EIC7700_CLK_MUX_CRYPTO_XTAL_2MUX1 72
+#define EIC7700_CLK_MUX_RMII_REF_2MUX 73
+#define EIC7700_CLK_MUX_ETH_CORE_2MUX1 74
+#define EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1 75
+#define EIC7700_CLK_MUX_VI_DW_XTAL_2MUX1 76
+#define EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE 77
+#define EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE 78
+#define EIC7700_CLK_DIV_SYS_CFG_DYNM 79
+#define EIC7700_CLK_DIV_NOC_NSP_DYNM 80
+#define EIC7700_CLK_DIV_BOOTSPI_DYNM 81
+#define EIC7700_CLK_DIV_SCPU_CORE_DYNM 82
+#define EIC7700_CLK_DIV_LPCPU_CORE_DYNM 83
+#define EIC7700_CLK_DIV_GPU_ACLK_DYNM 84
+#define EIC7700_CLK_DIV_DSP_ACLK_DYNM 85
+#define EIC7700_CLK_DIV_D2D_ACLK_DYNM 86
+#define EIC7700_CLK_DIV_HSP_ACLK_DYNM 87
+#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0 88
+#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1 89
+#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_0 90
+#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_1 91
+#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_2 92
+#define EIC7700_CLK_DIV_PCIE_ACLK_DYNM 93
+#define EIC7700_CLK_DIV_NPU_ACLK_DYNM 94
+#define EIC7700_CLK_DIV_NPU_LLC_SRC0_DYNM 95
+#define EIC7700_CLK_DIV_NPU_LLC_SRC1_DYNM 96
+#define EIC7700_CLK_DIV_NPU_CORECLK_DYNM 97
+#define EIC7700_CLK_DIV_VI_ACLK_DYNM 98
+#define EIC7700_CLK_DIV_VI_DVP_DYNM 99
+#define EIC7700_CLK_DIV_VI_DIG_ISP_DYNM 100
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0 101
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1 102
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2 103
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3 104
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4 105
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5 106
+#define EIC7700_CLK_DIV_VO_ACLK_DYNM 107
+#define EIC7700_CLK_DIV_IESMCLK_DYNM 108
+#define EIC7700_CLK_DIV_VO_PIXEL_DYNM 109
+#define EIC7700_CLK_DIV_VO_MCLK_DYNM 110
+#define EIC7700_CLK_DIV_VC_ACLK_DYNM 111
+#define EIC7700_CLK_DIV_JD_DYNM 112
+#define EIC7700_CLK_DIV_JE_DYNM 113
+#define EIC7700_CLK_DIV_VE_DYNM 114
+#define EIC7700_CLK_DIV_VD_DYNM 115
+#define EIC7700_CLK_DIV_G2D_DYNM 116
+#define EIC7700_CLK_DIV_AONDMA_AXI_DYNM 117
+#define EIC7700_CLK_DIV_CRYPTO_DYNM 118
+#define EIC7700_CLK_DIV_VI_DW_DYNM 119
+#define EIC7700_CLK_DIV_NPU_E31_DYNM 120
+#define EIC7700_CLK_DIV_SATA_PHY_REF_DYNM 121
+#define EIC7700_CLK_DIV_DSP_0_ACLK_DYNM 122
+#define EIC7700_CLK_DIV_DSP_1_ACLK_DYNM 123
+#define EIC7700_CLK_DIV_DSP_2_ACLK_DYNM 124
+#define EIC7700_CLK_DIV_DSP_3_ACLK_DYNM 125
+#define EIC7700_CLK_DIV_DDR_ACLK_DYNM 126
+#define EIC7700_CLK_DIV_AON_RTC_DYNM 127
+#define EIC7700_CLK_DIV_U84_RTC_TOGGLE_DYNM 128
+#define EIC7700_CLK_DIV_VO_CEC_DYNM 129
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_0 130
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_1 131
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_2 132
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_3 133
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_0 134
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_1 135
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_2 136
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_3 137
+#define EIC7700_CLK_GATE_CPU_DEBUG_CLK 138
+#define EIC7700_CLK_GATE_CPU_TRACE_COM_CLK 139
+#define EIC7700_CLK_GATE_CPU_CLK 140
+#define EIC7700_CLK_GATE_SPLL0_FOUT2 141
+#define EIC7700_CLK_GATE_VPLL_FOUT2 142
+#define EIC7700_CLK_GATE_VPLL_FOUT3 143
+#define EIC7700_CLK_GATE_APLL_FOUT1 144
+#define EIC7700_CLK_GATE_APLL_FOUT2 145
+#define EIC7700_CLK_GATE_APLL_FOUT3 146
+#define EIC7700_CLK_GATE_EXT_MCLK 147
+#define EIC7700_CLK_GATE_1M 148
+#define EIC7700_CLK_GATE_SYS_CFG 149
+#define EIC7700_CLK_GATE_MIPI_TXESC 150
+#define EIC7700_CLK_GATE_NOC_CFG_CLK 151
+#define EIC7700_CLK_GATE_NOC_NSP_CLK 152
+#define EIC7700_CLK_GATE_BOOTSPI 153
+#define EIC7700_CLK_GATE_BOOTSPI_CFG 154
+#define EIC7700_CLK_GATE_U84_CORE_LP 155
+#define EIC7700_CLK_GATE_SCPU_CORE 156
+#define EIC7700_CLK_GATE_SCPU_BUS 157
+#define EIC7700_CLK_GATE_LPCPU_CORE 158
+#define EIC7700_CLK_GATE_LPCPU_BUS 159
+#define EIC7700_CLK_GATE_GPU_ACLK 160
+#define EIC7700_CLK_GATE_GPU_GRAY_CLK 161
+#define EIC7700_CLK_GATE_GPU_CFG_CLK 162
+#define EIC7700_CLK_GATE_DSP_ROOT 163
+#define EIC7700_CLK_GATE_DSPT_ACLK 164
+#define EIC7700_CLK_GATE_DSPT_CFG_CLK 165
+#define EIC7700_CLK_GATE_D2DDR_ACLK 166
+#define EIC7700_CLK_GATE_D2D_ACLK 167
+#define EIC7700_CLK_GATE_D2D_CFG_CLK 168
+#define EIC7700_CLK_GATE_CLK_HSP_ACLK 169
+#define EIC7700_CLK_GATE_HSP_CFGCLK 170
+#define EIC7700_CLK_GATE_TCU_ACLK 171
+#define EIC7700_CLK_GATE_TCU_CFG_CLK 172
+#define EIC7700_CLK_GATE_DDRT_CFG_CLK 173
+#define EIC7700_CLK_GATE_DDRT1_CFG_CLK 174
+#define EIC7700_CLK_GATE_DDRT0_P0_ACLK 175
+#define EIC7700_CLK_GATE_DDRT0_P1_ACLK 176
+#define EIC7700_CLK_GATE_DDRT0_P2_ACLK 177
+#define EIC7700_CLK_GATE_DDRT0_P3_ACLK 178
+#define EIC7700_CLK_GATE_DDRT0_P4_ACLK 179
+#define EIC7700_CLK_GATE_DDRT1_P0_ACLK 180
+#define EIC7700_CLK_GATE_DDRT1_P1_ACLK 181
+#define EIC7700_CLK_GATE_DDRT1_P2_ACLK 182
+#define EIC7700_CLK_GATE_DDRT1_P3_ACLK 183
+#define EIC7700_CLK_GATE_DDRT1_P4_ACLK 184
+#define EIC7700_CLK_GATE_HSP_ACLK 185
+#define EIC7700_CLK_GATE_HSP_CFG_CLK 186
+#define EIC7700_CLK_GATE_HSP_SATA_RBC_CLK 187
+#define EIC7700_CLK_GATE_HSP_SATA_OOB_CLK 188
+#define EIC7700_CLK_GATE_HSP_SATA_PMALIVE_CLK 189
+#define EIC7700_CLK_GATE_HSP_ETH_APP_CLK 190
+#define EIC7700_CLK_GATE_HSP_ETH_CSR_CLK 191
+#define EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK 192
+#define EIC7700_CLK_GATE_HSP_ETH1_CORE_CLK 193
+#define EIC7700_CLK_GATE_HSP_MSHC0_CORE_CLK 194
+#define EIC7700_CLK_GATE_HSP_MSHC1_CORE_CLK 195
+#define EIC7700_CLK_GATE_HSP_MSHC2_CORE_CLK 196
+#define EIC7700_CLK_GATE_HSP_MSHC0_TMR_CLK 197
+#define EIC7700_CLK_GATE_HSP_MSHC1_TMR_CLK 198
+#define EIC7700_CLK_GATE_HSP_MSHC2_TMR_CLK 199
+#define EIC7700_CLK_GATE_HSP_USB0_SUSPEND_CLK 200
+#define EIC7700_CLK_GATE_HSP_USB1_SUSPEND_CLK 201
+#define EIC7700_CLK_GATE_PCIET_ACLK 202
+#define EIC7700_CLK_GATE_PCIET_CFG_CLK 203
+#define EIC7700_CLK_GATE_PCIET_CR_CLK 204
+#define EIC7700_CLK_GATE_PCIET_AUX_CLK 205
+#define EIC7700_CLK_GATE_NPU_ACLK 206
+#define EIC7700_CLK_GATE_NPU_CFG_CLK 207
+#define EIC7700_CLK_GATE_NPU_LLC_SRC0 208
+#define EIC7700_CLK_GATE_NPU_LLC_SRC1 209
+#define EIC7700_CLK_GATE_NPU_LLC_ACLK 210
+#define EIC7700_CLK_GATE_NPU_CORE_ST1 211
+#define EIC7700_CLK_GATE_NPU_CLK 212
+#define EIC7700_CLK_GATE_NPU_E31_CLK 213
+#define EIC7700_CLK_GATE_VI_ACLK_ST1 214
+#define EIC7700_CLK_GATE_VI_ACLK 215
+#define EIC7700_CLK_GATE_VI_DVP_CLK 216
+#define EIC7700_CLK_GATE_VI_CFG_CLK 217
+#define EIC7700_CLK_GATE_VI_DIG_DW_CLK 218
+#define EIC7700_CLK_GATE_VI_DIG_ISP_CLK 219
+#define EIC7700_CLK_GATE_VI_SHUTTER_0 220
+#define EIC7700_CLK_GATE_VI_SHUTTER_1 221
+#define EIC7700_CLK_GATE_VI_SHUTTER_2 222
+#define EIC7700_CLK_GATE_VI_SHUTTER_3 223
+#define EIC7700_CLK_GATE_VI_SHUTTER_4 224
+#define EIC7700_CLK_GATE_VI_SHUTTER_5 225
+#define EIC7700_CLK_GATE_VI_PHY_TXCLKESC 226
+#define EIC7700_CLK_GATE_VI_PHY_CFG 227
+#define EIC7700_CLK_GATE_VO_ACLK 228
+#define EIC7700_CLK_GATE_VO_CFG_CLK 229
+#define EIC7700_CLK_GATE_VO_HDMI_IESMCLK 230
+#define EIC7700_CLK_GATE_VO_PIXEL_CLK 231
+#define EIC7700_CLK_GATE_VO_I2S_MCLK 232
+#define EIC7700_CLK_GATE_VO_CR_CLK 233
+#define EIC7700_CLK_GATE_VO_CEC_CLK 234
+#define EIC7700_CLK_GATE_VC_ROOT 235
+#define EIC7700_CLK_GATE_VC_ACLK 236
+#define EIC7700_CLK_GATE_VC_CFG_CLK 237
+#define EIC7700_CLK_GATE_VC_JE_CLK 238
+#define EIC7700_CLK_GATE_VC_JD_CLK 239
+#define EIC7700_CLK_GATE_VC_VE_CLK 240
+#define EIC7700_CLK_GATE_VC_VD_CLK 241
+#define EIC7700_CLK_GATE_G2D_CFG_CLK 242
+#define EIC7700_CLK_GATE_G2D_ST2 243
+#define EIC7700_CLK_GATE_G2D_CLK 244
+#define EIC7700_CLK_GATE_G2D_ACLK 245
+#define EIC7700_CLK_GATE_PVT_INNER 246
+#define EIC7700_CLK_GATE_PVT_CLK_0 247
+#define EIC7700_CLK_GATE_PVT_CLK_1 248
+#define EIC7700_CLK_GATE_PVT_CLK_2 249
+#define EIC7700_CLK_GATE_PVT_CLK_3 250
+#define EIC7700_CLK_GATE_PVT_CLK_4 251
+#define EIC7700_CLK_GATE_AONDMA_CFG 252
+#define EIC7700_CLK_GATE_AONDMA_AXI_ST3 253
+#define EIC7700_CLK_GATE_AONDMA_ACLK 254
+#define EIC7700_CLK_GATE_AON_ACLK 255
+#define EIC7700_CLK_GATE_TIMER_CLK_0 256
+#define EIC7700_CLK_GATE_TIMER_CLK_1 257
+#define EIC7700_CLK_GATE_TIMER_CLK_2 258
+#define EIC7700_CLK_GATE_TIMER_CLK_3 259
+#define EIC7700_CLK_GATE_TIMER_PCLK_0 260
+#define EIC7700_CLK_GATE_TIMER_PCLK_1 261
+#define EIC7700_CLK_GATE_TIMER_PCLK_2 262
+#define EIC7700_CLK_GATE_TIMER_PCLK_3 263
+#define EIC7700_CLK_GATE_TIMER3_CLK8 264
+#define EIC7700_CLK_GATE_RTC_CFG 265
+#define EIC7700_CLK_GATE_RTC 266
+#define EIC7700_CLK_GATE_HSP_RMII_REF_0 267
+#define EIC7700_CLK_GATE_HSP_RMII_REF_1 268
+#define EIC7700_CLK_GATE_PKA_CFG 269
+#define EIC7700_CLK_GATE_SPACC_CFG 270
+#define EIC7700_CLK_GATE_CRYPTO 271
+#define EIC7700_CLK_GATE_TRNG_CFG 272
+#define EIC7700_CLK_GATE_OTP_CFG 273
+#define EIC7700_CLK_GATE_CLMM_CFG_CLK 274
+#define EIC7700_CLK_GATE_CLMM_DEB_CLK 275
+#define EIC7700_CLK_GATE_MAILBOX_0 276
+#define EIC7700_CLK_GATE_MAILBOX_1 277
+#define EIC7700_CLK_GATE_MAILBOX_2 278
+#define EIC7700_CLK_GATE_MAILBOX_3 279
+#define EIC7700_CLK_GATE_MAILBOX_4 280
+#define EIC7700_CLK_GATE_MAILBOX_5 281
+#define EIC7700_CLK_GATE_MAILBOX_6 282
+#define EIC7700_CLK_GATE_MAILBOX_7 283
+#define EIC7700_CLK_GATE_MAILBOX_8 284
+#define EIC7700_CLK_GATE_MAILBOX_9 285
+#define EIC7700_CLK_GATE_MAILBOX_10 286
+#define EIC7700_CLK_GATE_MAILBOX_11 287
+#define EIC7700_CLK_GATE_MAILBOX_12 288
+#define EIC7700_CLK_GATE_MAILBOX_13 289
+#define EIC7700_CLK_GATE_MAILBOX_14 290
+#define EIC7700_CLK_GATE_MAILBOX_15 291
+#define EIC7700_CLK_GATE_APLL_TEST_OUT 292
+#define EIC7700_CLK_GATE_CPLL_TEST_OUT 293
+#define EIC7700_CLK_GATE_HSP_DFT150M 294
+#define EIC7700_CLK_GATE_HSP_DFT300M 295
+#define EIC7700_CLK_GATE_HSP_DFT600M 296
+#define EIC7700_CLK_GATE_VI_DFT400M 297
+#define EIC7700_CLK_GATE_VI_DFT500M 298
+#define EIC7700_CLK_GATE_VO_DFT300M 299
+#define EIC7700_CLK_GATE_VO_DFT600M 300
+#define EIC7700_CLK_GATE_D2D_DFT300M 301
+#define EIC7700_CLK_GATE_D2D_DFT600M 302
+#define EIC7700_CLK_GATE_PCIE_DFT125M 303
+#define EIC7700_CLK_GATE_PCIE_DFT200M 304
+#define EIC7700_CLK_GATE_DDR_PLL_BYP_CLK 305
+#define EIC7700_CLK_GATE_DDR_RX_TEST_CLK 306
+#define EIC7700_CLK_GATE_LSP_I2C0_PCLK 307
+#define EIC7700_CLK_GATE_LSP_I2C1_PCLK 308
+#define EIC7700_CLK_GATE_LSP_I2C2_PCLK 309
+#define EIC7700_CLK_GATE_LSP_I2C3_PCLK 310
+#define EIC7700_CLK_GATE_LSP_I2C4_PCLK 311
+#define EIC7700_CLK_GATE_LSP_I2C5_PCLK 312
+#define EIC7700_CLK_GATE_LSP_I2C6_PCLK 313
+#define EIC7700_CLK_GATE_LSP_I2C7_PCLK 314
+#define EIC7700_CLK_GATE_LSP_I2C8_PCLK 315
+#define EIC7700_CLK_GATE_LSP_I2C9_PCLK 316
+#define EIC7700_CLK_GATE_LSP_WDT0_PCLK 317
+#define EIC7700_CLK_GATE_LSP_WDT1_PCLK 318
+#define EIC7700_CLK_GATE_LSP_WDT2_PCLK 319
+#define EIC7700_CLK_GATE_LSP_WDT3_PCLK 320
+#define EIC7700_CLK_GATE_LSP_SSI0_PCLK 321
+#define EIC7700_CLK_GATE_LSP_SSI1_PCLK 322
+#define EIC7700_CLK_GATE_LSP_PVT_PCLK 323
+#define EIC7700_CLK_GATE_AON_I2C0_PCLK 324
+#define EIC7700_CLK_GATE_AON_I2C1_PCLK 325
+#define EIC7700_CLK_GATE_LSP_UART0_PCLK 326
+#define EIC7700_CLK_GATE_LSP_UART1_PCLK 327
+#define EIC7700_CLK_GATE_LSP_UART2_PCLK 328
+#define EIC7700_CLK_GATE_LSP_UART3_PCLK 329
+#define EIC7700_CLK_GATE_LSP_UART4_PCLK 330
+#define EIC7700_CLK_GATE_LSP_TIMER_PCLK 331
+#define EIC7700_CLK_GATE_LSP_FAN_PCLK 332
+#define EIC7700_CLK_GATE_LSP_PVT0_CLK 333
+#define EIC7700_CLK_GATE_LSP_PVT1_CLK 334
+#define EIC7700_CLK_GATE_VC_JE_PCLK 335
+#define EIC7700_CLK_GATE_VC_JD_PCLK 336
+#define EIC7700_CLK_GATE_VC_VE_PCLK 337
+#define EIC7700_CLK_GATE_VC_VD_PCLK 338
+#define EIC7700_CLK_GATE_VC_MON_PCLK 339
+#define EIC7700_CLK_GATE_HSP_DMA0_CLK 340
+#define EIC7700_CLK_GATE_HSP_DMA0_CLK_TEST 341
+#define EIC7700_CLK_FIXED_FACTOR_CPU_DIV2 342
+#define EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24 343
+#define EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10 344
+#define EIC7700_CLK_FIXED_FACTOR_U84_CORE_LP_DIV2 345
+#define EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2 346
+#define EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2 347
+#define EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2 348
+#define EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4 349
+#define EIC7700_CLK_FIXED_FACTOR_PVT_DIV20 350
+#define EIC7700_CLK_FIXED_FACTOR_DFT100M_DIV4 351
+#define EIC7700_CLK_FIXED_FACTOR_DFT125M_DIV2 352
+#define EIC7700_CLK_FIXED_FACTOR_DFT150M_DIV2 353
+#define EIC7700_CLK_FIXED_FACTOR_DFT100M_DIV2 354
+#define EIC7700_CLK_FIXED_FACTOR_DFT500M_DIV3 355
+#define EIC7700_CLK_FIXED_FACTOR_DFT500M_DIV2 356
+#define EIC7700_CLK_FIXED_FACTOR_SPLL0_TEST_DIV8 357
+#define EIC7700_CLK_FIXED_FACTOR_SPLL1_TEST_DIV6 358
+#define EIC7700_CLK_FIXED_FACTOR_SPLL2_TEST_DIV4 359
+#define EIC7700_CLK_FIXED_FACTOR_DDR_DIV8 360
+#define EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6 361
+
+#endif /* _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ */
--
2.43.0
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