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Message-ID: <798600a43825818bcf828da7060f38105f7f3225.camel@linaro.org>
Date: Wed, 24 Sep 2025 17:00:31 +0100
From: André Draszik <andre.draszik@...aro.org>
To: Tudor Ambarus <tudor.ambarus@...aro.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Peter Griffin <peter.griffin@...aro.org>, Michael
Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
Krzysztof Kozlowski <krzk@...nel.org>, Alim Akhtar
<alim.akhtar@...sung.com>, Sylwester Nawrocki <s.nawrocki@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>, Catalin Marinas
<catalin.marinas@....com>, Will Deacon <will@...nel.org>
Cc: linux-kernel@...r.kernel.org, linux-samsung-soc@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-clk@...r.kernel.org, willmcvicker@...gle.com, kernel-team@...roid.com
Subject: Re: [PATCH v5 4/5] clk: samsung: add Exynos ACPM clock driver
Hi Tudor,
On Wed, 2025-09-24 at 15:11 +0000, Tudor Ambarus wrote:
> Add the Exynos ACPM clock driver. It provides support for clocks that
> are controlled by firmware that implements the ACPM interface.
[...]
> diff --git a/drivers/clk/samsung/clk-acpm.c b/drivers/clk/samsung/clk-acpm.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..9e8354168a63b1427c2f3faf15e4e7955e924dc8
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-acpm.c
> @@ -0,0 +1,185 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Samsung Exynos ACPM protocol based clock driver.
> + *
> + * Copyright 2025 Linaro Ltd.
> + */
> +
> +#include <linux/array_size.h>
> +#include <linux/clk-provider.h>
> +#include <linux/container_of.h>
> +#include <linux/device/devres.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/firmware/samsung/exynos-acpm-protocol.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/types.h>
> +
> +struct acpm_clk {
> + u32 id;
> + struct clk_hw hw;
> + unsigned int mbox_chan_id;
> + const struct acpm_handle *handle;
> +};
> +
> +struct acpm_clk_variant {
> + const char *name;
> +};
> +
> +struct acpm_clk_driver_data {
> + const struct acpm_clk_variant *clks;
> + unsigned int nr_clks;
> + unsigned int mbox_chan_id;
> +};
> +
> +#define to_acpm_clk(clk) container_of(clk, struct acpm_clk, hw)
> +
> +#define ACPM_CLK(cname) \
> + { \
> + .name = cname, \
> + }
> +
> +static const struct acpm_clk_variant gs101_acpm_clks[] = {
> + ACPM_CLK("mif"),
> + ACPM_CLK("int"),
> + ACPM_CLK("cpucl0"),
> + ACPM_CLK("cpucl1"),
> + ACPM_CLK("cpucl2"),
> + ACPM_CLK("g3d"),
> + ACPM_CLK("g3dl2"),
> + ACPM_CLK("tpu"),
> + ACPM_CLK("intcam"),
> + ACPM_CLK("tnr"),
> + ACPM_CLK("cam"),
> + ACPM_CLK("mfc"),
> + ACPM_CLK("disp"),
> + ACPM_CLK("b0"),
The last one should be 'bo' (bigocean), not b0.
Cheers,
Andre'
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