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Message-ID: <20250924160414.GA1780679-robh@kernel.org>
Date: Wed, 24 Sep 2025 11:04:14 -0500
From: Rob Herring <robh@...nel.org>
To: Pankaj Patil <pankaj.patil@....qualcomm.com>
Cc: sboyd@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH] dt-bindings: spmi: add bindings for glymur-spmi-pmic-arb
(arbiter v8)
On Fri, Sep 19, 2025 at 07:39:52PM +0530, Pankaj Patil wrote:
> From: Jishnu Prakash <jishnu.prakash@....qualcomm.com>
>
> SPMI PMIC Arbiter version 8 builds upon version 7 with support for
> up to four SPMI buses. To achieve this, the register map was
> slightly rearranged. Add a new binding file and compatible string
> for version 8 using the name 'glymur' as the Qualcomm Technologies,
> Inc. Glymur SoC is the first one to use PMIC arbiter version 8. This
> specifies the new register ranges needed only for version 8.
>
> Signed-off-by: David Collins <david.collins@....qualcomm.com>
> Signed-off-by: Jishnu Prakash <jishnu.prakash@....qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
> ---
> .../spmi/qcom,glymur-spmi-pmic-arb.yaml | 158 ++++++++++++++++++
> 1 file changed, 158 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml
>
> diff --git a/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml b/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml
> new file mode 100644
> index 000000000000..e80997a5fb4b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml
> @@ -0,0 +1,158 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spmi/qcom,glymur-spmi-pmic-arb.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Technologies, Inc. Glymur SPMI Controller (PMIC Arbiter v8)
> +
> +maintainers:
> + - Stephen Boyd <sboyd@...nel.org>
> +
> +description: |
> + The Glymur SPMI PMIC Arbiter implements HW version 8 and it's an SPMI
> + controller with wrapping arbitration logic to allow for multiple on-chip
> + devices to control up to 4 SPMI separate buses.
> +
> + The PMIC Arbiter can also act as an interrupt controller, providing interrupts
> + to slave devices.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,glymur-spmi-pmic-arb
> +
> + reg:
> + items:
> + - description: core registers
> + - description: tx-channel per virtual slave registers
> + - description: rx-channel (called observer) per virtual slave registers
> + - description: channel to PMIC peripheral mapping registers
> +
> + reg-names:
> + items:
> + - const: core
> + - const: chnls
> + - const: obsrvr
> + - const: chnl_map
> +
> + ranges: true
> +
> + '#address-cells':
> + const: 2
> +
> + '#size-cells':
> + const: 2
> +
> + qcom,ee:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 5
> + description: >
> + indicates the active Execution Environment identifier
> +
> + qcom,channel:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 5
> + description: >
> + which of the PMIC Arb provided channels to use for accesses
We already have these properties defined elsewhere. You need to pull the
common properties out into a shared schema and then reference that
schema in this one. IOW, a given property should only have a type $ref
in a single place.
> +
> +patternProperties:
> + "^spmi@[a-f0-9]+$":
> + type: object
> + $ref: /schemas/spmi/spmi.yaml
> + unevaluatedProperties: false
> +
> + properties:
> + reg:
> + items:
> + - description: configuration registers
> + - description: interrupt controller registers
> + - description: channel owner EE mapping registers
> +
> + reg-names:
> + items:
> + - const: cnfg
> + - const: intr
> + - const: chnl_owner
> +
> + interrupts:
> + maxItems: 1
> +
> + interrupt-names:
> + const: periph_irq
> +
> + interrupt-controller: true
> +
> + '#interrupt-cells':
> + const: 4
> + description: |
> + cell 1: slave ID for the requested interrupt (0-15)
> + cell 2: peripheral ID for requested interrupt (0-255)
> + cell 3: the requested peripheral interrupt (0-7)
> + cell 4: interrupt flags indicating level-sense information,
> + as defined in dt-bindings/interrupt-controller/irq.h
> +
> +required:
> + - compatible
> + - reg-names
> + - qcom,ee
> + - qcom,channel
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + arbiter@...0000 {
> + compatible = "qcom,glymur-spmi-pmic-arb";
> + reg = <0x0 0xc400000 0x0 0x3000>,
> + <0x0 0xc900000 0x0 0x400000>,
> + <0x0 0xc4c0000 0x0 0x400000>,
> + <0x0 0xc403000 0x0 0x8000>;
> + reg-names = "core", "chnls", "obsrvr", "chnl_map";
> +
> + qcom,ee = <0>;
> + qcom,channel = <0>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + spmi@...6000 {
> + reg = <0x0 0xc426000 0x0 0x4000>,
> + <0x0 0xc8c0000 0x0 0x10000>,
> + <0x0 0xc42a000 0x0 0x8000>;
> + reg-names = "cnfg", "intr", "chnl_owner";
> +
> + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "periph_irq";
> + interrupt-controller;
> + #interrupt-cells = <4>;
> +
> + #address-cells = <2>;
> + #size-cells = <0>;
> + };
> +
> + spmi@...7000 {
> + reg = <0x0 0xc437000 0x0 0x4000>,
> + <0x0 0xc8d0000 0x0 0x10000>,
> + <0x0 0xc43b000 0x0 0x8000>;
> + reg-names = "cnfg", "intr", "chnl_owner";
> +
> + interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "periph_irq";
> + interrupt-controller;
> + #interrupt-cells = <4>;
> +
> + #address-cells = <2>;
> + #size-cells = <0>;
> + };
> + };
> + };
> --
> 2.34.1
>
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