linux-kernel - Re: [PATCH v2 08/10] nova-core: falcon: Add support to check if RISC-V is active

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Message-ID: <d067b6a45722c763b5c5434a276eb416faff03b8.camel@redhat.com>
Date: Wed, 24 Sep 2025 18:12:44 -0400
From: Lyude Paul <lyude@...hat.com>
To: Alistair Popple <apopple@...dia.com>, rust-for-linux@...r.kernel.org, 
	dri-devel@...ts.freedesktop.org, dakr@...nel.org, acourbot@...dia.com
Cc: Miguel Ojeda <ojeda@...nel.org>, Alex Gaynor <alex.gaynor@...il.com>, 
 Boqun Feng <boqun.feng@...il.com>, Gary Guo <gary@...yguo.net>,
 Björn Roy Baron	 <bjorn3_gh@...tonmail.com>, Benno
 Lossin <lossin@...nel.org>, Andreas Hindborg	 <a.hindborg@...nel.org>,
 Alice Ryhl <aliceryhl@...gle.com>, Trevor Gross	 <tmgross@...ch.edu>, David
 Airlie <airlied@...il.com>, Simona Vetter	 <simona@...ll.ch>, Maarten
 Lankhorst <maarten.lankhorst@...ux.intel.com>,  Maxime Ripard
 <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>, John Hubbard
 <jhubbard@...dia.com>,  Joel Fernandes <joelagnelf@...dia.com>, Timur Tabi
 <ttabi@...dia.com>, linux-kernel@...r.kernel.org, 
	nouveau@...ts.freedesktop.org
Subject: Re: [PATCH v2 08/10] nova-core: falcon: Add support to check if
 RISC-V is active

Reviewed-by: Lyude Paul <lyude@...hat.com>

On Mon, 2025-09-22 at 21:30 +1000, Alistair Popple wrote:
> From: Joel Fernandes <joelagnelf@...dia.com>
> 
> Add definition for RISCV_CPUCTL register and use it in a new falcon API
> to check if the RISC-V core of a Falcon is active. It is required by
> the sequencer to know if the GSP's RISCV processor is active.
> 
> Signed-off-by: Joel Fernandes <joelagnelf@...dia.com>
> ---
>  drivers/gpu/nova-core/falcon.rs | 9 +++++++++
>  drivers/gpu/nova-core/regs.rs   | 5 +++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs
> index 37e6298195e4..c7907f16bcf4 100644
> --- a/drivers/gpu/nova-core/falcon.rs
> +++ b/drivers/gpu/nova-core/falcon.rs
> @@ -610,4 +610,13 @@ pub(crate) fn signature_reg_fuse_version(
>          self.hal
>              .signature_reg_fuse_version(self, bar, engine_id_mask, ucode_id)
>      }
> +
> +    /// Check if the RISC-V core is active.
> +    ///
> +    /// Returns `true` if the RISC-V core is active, `false` otherwise.
> +    #[expect(unused)]
> +    pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> Result<bool> {
> +        let cpuctl = regs::NV_PRISCV_RISCV_CPUCTL::read(bar, &E::ID);
> +        Ok(cpuctl.active_stat())
> +    }
>  }
> diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
> index 0585699ae951..5df6a2bf42ad 100644
> --- a/drivers/gpu/nova-core/regs.rs
> +++ b/drivers/gpu/nova-core/regs.rs
> @@ -324,6 +324,11 @@ pub(crate) fn mem_scrubbing_done(self) -> bool {
>  
>  // PRISCV
>  
> +register!(NV_PRISCV_RISCV_CPUCTL @ PFalconBase[0x00001388] {
> +    7:7     active_stat as bool;
> +    0:0     halted as bool;
> +});
> +
>  register!(NV_PRISCV_RISCV_BCR_CTRL @ PFalconBase[0x00001668] {
>      0:0     valid as bool;
>      4:4     core_select as bool => PeregrineCoreSelect;

-- 
Cheers,
 Lyude Paul (she/her)
 Software Engineer at Red Hat

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