linux-kernel - [PATCH v6 1/4] PCI: dwc: Remove the L1SS check before putting the link into L2

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Message-Id: <20250924072324.3046687-2-hongxing.zhu@nxp.com>
Date: Wed, 24 Sep 2025 15:23:21 +0800
From: Richard Zhu <hongxing.zhu@....com>
To: frank.li@....com,
	jingoohan1@...il.com,
	l.stach@...gutronix.de,
	lpieralisi@...nel.org,
	kwilczynski@...nel.org,
	mani@...nel.org,
	robh@...nel.org,
	bhelgaas@...gle.com,
	shawnguo@...nel.org,
	s.hauer@...gutronix.de,
	kernel@...gutronix.de,
	festevam@...il.com
Cc: linux-pci@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org,
	imx@...ts.linux.dev,
	linux-kernel@...r.kernel.org,
	Richard Zhu <hongxing.zhu@....com>,
	stable@...r.kernel.org,
	Bjorn Helgaas <helgaas@...nel.org>
Subject: [PATCH v6 1/4] PCI: dwc: Remove the L1SS check before putting the link into L2

The ASPM configuration shouldn't leak out here. Remove the L1SS check
during L2 entry.

Cc: stable@...r.kernel.org
Fixes: 4774faf854f5 ("PCI: dwc: Implement generic suspend/resume functionality")
Suggested-by: Bjorn Helgaas <helgaas@...nel.org>
Signed-off-by: Richard Zhu <hongxing.zhu@....com>
---
 drivers/pci/controller/dwc/pcie-designware-host.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 952f8594b501..9d46d1f0334b 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -1005,17 +1005,9 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci)
 
 int dw_pcie_suspend_noirq(struct dw_pcie *pci)
 {
-	u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
 	u32 val;
 	int ret;
 
-	/*
-	 * If L1SS is supported, then do not put the link into L2 as some
-	 * devices such as NVMe expect low resume latency.
-	 */
-	if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1)
-		return 0;
-
 	if (pci->pp.ops->pme_turn_off) {
 		pci->pp.ops->pme_turn_off(&pci->pp);
 	} else {
-- 
2.37.1