linux-kernel - Re: [PATCH 1/9] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Glymur compatible

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <483e0f79-1725-435b-830c-9c1dba886186@oss.qualcomm.com>
Date: Wed, 24 Sep 2025 14:31:19 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Wesley Cheng <wesley.cheng@....qualcomm.com>,
        Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
Cc: krzk+dt@...nel.org, conor+dt@...nel.org, kishon@...nel.org,
        vkoul@...nel.org, gregkh@...uxfoundation.org, robh@...nel.org,
        linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-usb@...r.kernel.org,
        linux-phy@...ts.infradead.org
Subject: Re: [PATCH 1/9] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add
 Glymur compatible

On 9/22/25 10:52 PM, Wesley Cheng wrote:
> 
> 
> On 9/20/2025 8:18 AM, Dmitry Baryshkov wrote:
>> On Fri, Sep 19, 2025 at 08:21:00PM -0700, Wesley Cheng wrote:
>>> Define a Glymur compatible string for the QMP PHY combo driver, along with
>>> resource requirements.  Add a different identifier for the primary QMP PHY
>>> instance as it does not require a clkref entry.
>>
>> Are register programming the same for both of them or not? If it's the
>> same, it might be not necessary to have different compatibles.
>>
> 
> Hi Dmitry,
> 
> Yes, the register programming sequences are the same, but the number of clocks are different between the primary and the other controllers. Specifically, on the primary USB controller, we don't have a clkref in the TCSR.  Was just adding a separate compatible ID to define the max clock items.  However, I do see that even if I only need 4 clks (for the primary) it technically doesn't break the DT bindings definition, as minItems = 4 and maxItems = 5 for the clock and clock-names fields.

We can just stick &xo_board in there and avoid the mess

XO physically supplies the PHY even if it's not programmatically
configurable like other gate/branch clocks

Konrad