linux-kernel - Re: [PATCH] soc: renesas: rz-sysc: Populate readable_reg/writeable

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Message-ID: <CAMuHMdV62NUeEYyYgf4LJ2JQLwA-fAzYyA-cy9h_nyYKmtB=1g@mail.gmail.com>
Date: Thu, 25 Sep 2025 16:05:49 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Claudiu <claudiu.beznea@...on.dev>
Cc: magnus.damm@...il.com, john.madieu.xa@...renesas.com, 
	linux-renesas-soc@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: Re: [PATCH] soc: renesas: rz-sysc: Populate readable_reg/writeable_reg
 in regmap config

Hi Claudiu,

On Mon, 22 Sept 2025 at 09:41, Claudiu <claudiu.beznea@...on.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
>
> Not all system controller registers are accessible from Linux. Accessing
> such registers generates synchronous external abort. Populate the
> readable_reg and writeable_reg members of the regmap config to inform the
> regmap core which registers can be accessed. The list will need to be
> updated whenever new system controller functionality is exported through
> regmap.
>
> Fixes: 2da2740fb9c8 ("soc: renesas: rz-sysc: Add syscon/regmap support")
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>

Thanks for your patch!

> --- a/drivers/soc/renesas/r9a08g045-sysc.c
> +++ b/drivers/soc/renesas/r9a08g045-sysc.c
> @@ -6,10 +6,14 @@
>   */
>
>  #include <linux/bits.h>
> +#include <linux/device.h>
>  #include <linux/init.h>
>
>  #include "rz-sysc.h"
>
> +#define SYS_USB_PWRRDY         0xd70
> +#define SYS_PCIE_RST_RSM_B     0xd74
> +
>  static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initconst = {
>         .family = "RZ/G3S",
>         .id = 0x85e0447,
> @@ -18,7 +22,20 @@ static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initc
>         .specific_id_mask = GENMASK(27, 0),
>  };
>
> +static bool rzg3s_regmap_readable_reg(struct device *dev, unsigned int reg)
> +{
> +       switch (reg) {
> +       case SYS_USB_PWRRDY:
> +       case SYS_PCIE_RST_RSM_B:

Given upstream has already support for RZ/G3S Ethernet, it may be wise
to add the GEther0/1 Config Registers at 0x380/0x390, too.  That way
you avoid a possible future hard dependency and regression when adding
support for configuring that register from the Ethernet driver.
The same is true for RZ/G3E, RZ/V2H, and RZ/V2N.

> +               return true;
> +       default:
> +               return false;
> +       }
> +}
> +
>  const struct rz_sysc_init_data rzg3s_sysc_init_data __initconst = {
>         .soc_id_init_data = &rzg3s_sysc_soc_id_init_data,
> +       .readable_reg = rzg3s_regmap_readable_reg,
> +       .writeable_reg = rzg3s_regmap_readable_reg,
>         .max_register = 0xe20,
>  };

> --- a/drivers/soc/renesas/r9a09g056-sys.c
> +++ b/drivers/soc/renesas/r9a09g056-sys.c
> @@ -70,6 +70,13 @@ static const struct rz_sysc_soc_id_init_data rzv2n_sys_soc_id_init_data __initco
>         .print_id = rzv2n_sys_print_id,
>  };
>
> +static bool rzv2n_regmap_readable_reg(struct device *dev, unsigned int reg)
> +{
> +       return false;

I would already add the TRU trimming registers, also for RZ/V2H, as
they can probably just reuse the RZ/G3E TSU driver.

> +}
> +
>  const struct rz_sysc_init_data rzv2n_sys_init_data = {
>         .soc_id_init_data = &rzv2n_sys_soc_id_init_data,
> +       .readable_reg = rzv2n_regmap_readable_reg,
> +       .writeable_reg = rzv2n_regmap_readable_reg,

Oops, this one does not have ".max_register = 0x170c" yet.
Does this cause any ill effects that warrant an urgent fix?

>  };

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds