lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <bugtpjwk77lcpa4jjox62ulmy56nf6yykzpr2ryifqqpeig6gp@45lzpngcpo2z>
Date: Thu, 25 Sep 2025 12:06:40 -0500
From: Bjorn Andersson <andersson@...nel.org>
To: Krzysztof Kozlowski <krzk@...nel.org>
Cc: Pankaj Patil <pankaj.patil@....qualcomm.com>, 
	Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Sibi Sankar <sibi.sankar@....qualcomm.com>
Subject: Re: [PATCH 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox

On Thu, Sep 25, 2025 at 05:23:07PM +0900, Krzysztof Kozlowski wrote:
> On Thu, 25 Sept 2025 at 15:33, Pankaj Patil
> <pankaj.patil@....qualcomm.com> wrote:
> >
> > From: Sibi Sankar <sibi.sankar@....qualcomm.com>
> >
> > Enable pdp0 mailbox node on Glymur SoCs.
> >
> > Signed-off-by: Sibi Sankar <sibi.sankar@....qualcomm.com>
> > Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
> > ---
> >  arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > index 66a548400c720474cde8a8b82ee686be507a795f..ae013c64e096b7c90c0aa4cfc50f078a85518acb 100644
> > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > @@ -4065,6 +4065,14 @@ watchdog@...00000 {
> >                         interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
> >                 };
> >
> > +               pdp0_mbox: mailbox@...10000 {
> > +                       compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
> > +                       reg = <0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>;
> > +                       interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> > +                       #mbox-cells = <1>;
> > +                       qcom,rx-chans = <0x7>;
> > +               };
> 
> Again one node per patch. this is really pointless, please read
> submitting patches before posting.
> 

In this series I certainly agree with you.

This is most definitely part of the next patch, which is core support
that should have been part of the introduction of the CPU nodes in the
initial patch.

Regards,
Bjorn

> New Soc is one logical change. One.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ