linux-kernel - Re: [PATCH RESEND v1 i2c-master] i2c: mchp-pci1xxxx: PCIe Hot reset disable support for Rev C0+ devices

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <aNWnOOg5KY_8K1DO@shikoro>
Date: Thu, 25 Sep 2025 22:34:00 +0200
From: Wolfram Sang <wsa+renesas@...g-engineering.com>
To: Rengarajan S <rengarajan.s@...rochip.com>
Cc: tharunkumar.pasumarthi@...rochip.com,
	kumaravel.thiagarajan@...rochip.com, UNGLinuxDriver@...rochip.com,
	andi.shyti@...nel.org, linux-i2c@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH RESEND v1 i2c-master] i2c: mchp-pci1xxxx: PCIe Hot reset
 disable support for Rev C0+ devices

On Thu, Sep 25, 2025 at 07:30:48PM +0530, Rengarajan S wrote:
> Systems that issue PCIe hot reset requests during a suspend/resume
> cycle cause PCI1XXXX device revisions prior to C0 to get its SMBUS
> controller registers reset to hardware default values. This results
> in device inaccessibility and I2C read/write failure. Starting with
> Revision C0, support was added in the device hardware (via the Hot
> Reset Disable Bit) to allow resetting only the PCIe interface and its
> associated logic, but preserving the SMBUS registers during a hot
> reset. This patch enables the hot reset disable feature during suspend/
> resume for C0 and later revisions of the device.
> 
> Signed-off-by: Rengarajan S <rengarajan.s@...rochip.com>

Tharun? Kumaravel? Do you have time to look at these patches?


Download attachment "signature.asc" of type "application/pgp-signature" (834 bytes)