linux-kernel - Re: [PATCH v2 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines

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Message-ID: <dmuhltvj5shmysyjmzjhf6q6nvng45odpwbxsi7frmziunxtgq@xppf6cpyqt2r>
Date: Fri, 26 Sep 2025 00:16:41 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Pankaj Patil <pankaj.patil@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>
Subject: Re: [PATCH v2 04/24] arm64: dts: qcom: glymur: Add QUPv3
 configuration for serial engines

On Thu, Sep 25, 2025 at 11:58:10AM +0530, Pankaj Patil wrote:
> From: Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>
> 
> Add device tree support for QUPv3 serial engine protocols on Glymur.
> Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
> support of GPI DMA engines.
> 
> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/glymur-crd.dts |   43 +
>  arch/arm64/boot/dts/qcom/glymur.dtsi    | 3041 +++++++++++++++++++++++++++++--
>  2 files changed, 2936 insertions(+), 148 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> index a1714ec8492961b211ec761f16b39245007533b8..4561c0b87b017cba0a1db8814123a070b37fd434 100644
> --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> @@ -13,6 +13,49 @@ / {
>  
>  	aliases {
>  		serial0 = &uart21;
> +		serial1 = &uart14;
> +		i2c0 = &i2c16;
> +		i2c1 = &i2c17;
> +		i2c2 = &i2c18;
> +		i2c3 = &i2c19;
> +		i2c4 = &i2c20;
> +		i2c5 = &i2c22;
> +		i2c6 = &i2c23;
> +		i2c7 = &i2c8;
> +		i2c8 = &i2c9;
> +		i2c9 = &i2c10;
> +		i2c10 = &i2c11;
> +		i2c11 = &i2c12;
> +		i2c12 = &i2c13;
> +		i2c13 = &i2c15;
> +		i2c14 = &i2c0;
> +		i2c15 = &i2c1;
> +		i2c16 = &i2c2;
> +		i2c17 = &i2c3;
> +		i2c18 = &i2c4;
> +		i2c19 = &i2c5;
> +		i2c20 = &i2c6;
> +		spi0 = &spi16;
> +		spi1 = &spi17;
> +		spi2 = &spi18;
> +		spi3 = &spi19;
> +		spi4 = &spi20;
> +		spi5 = &spi22;
> +		spi6 = &spi23;
> +		spi7 = &spi8;
> +		spi8 = &spi9;
> +		spi9 = &spi10;
> +		spi10 = &spi11;
> +		spi11 = &spi12;
> +		spi12 = &spi13;
> +		spi13 = &spi15;
> +		spi14 = &spi0;
> +		spi15 = &spi1;
> +		spi16 = &spi2;
> +		spi17 = &spi3;
> +		spi18 = &spi4;
> +		spi19 = &spi5;
> +		spi20 = &spi6;

This is a very weird numbering. Could you please add a comment,
explaining it?

>  	};
>  
>  	chosen {
-- 
With best wishes
Dmitry